參數(shù)資料
型號: CS42L51-DNZ
廠商: Cirrus Logic Inc
文件頁數(shù): 27/43頁
文件大小: 0K
描述: IC CODEC STEREO W/HDPN AMP 32QFN
標(biāo)準(zhǔn)包裝: 60
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 98 / 98
電壓 - 電源,模擬: 1.8V,2.5V
電壓 - 電源,數(shù)字: 1.8V,2.5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-QFN
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
配用: 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC
其它名稱: 598-1627
DS679F1
33
CS42L51
4.3.8
Noise Gate
The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents
the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before
the noise gate attacks the signal.
Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC pre-am-
plifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied, the max-
imum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.
Ramp-down time to the maximum setting is affected by the SOFTx bit.
Recommended settings: For best results, enable soft ramp for the digital attenuator. When the analog in-
puts are configured for differential signals (see “Differential Inputs” on page 29), enable the NG_ALL bit
to trigger the noise gate only when both inputs fall below the threshold.
Software
Controls:
-96
-40
THRESH[2:0]
Max
imum
A
tt
e
n
u
a
ti
o
n
*
-52 dB
Output
(dB)
Input (dB)
N
G
E
N
=1
N
G
E
N
=0
-80 dB
-64 dB
Figure 12. Noise Gate Attenuation
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