The idle (TI) state indicates that no data transfers are in
參數(shù)資料
型號(hào)： CS80C286-12
廠商： Intersil
文件頁(yè)數(shù)： 21/60頁(yè)
文件大?。?/td> 0K
描述： IC CPU 16BIT 5V 12.5MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 126
處理器類型： 80C286 16-位
速度： 12.5MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC（24.23x24.23）
包裝： 管件
28
Bus States
The idle (TI) state indicates that no data transfers are in
progress or requested. The first active state TS is signaled
by status line S1 or S0 going LOW and identifying phase 1 of
the processor clock. During TS, the command encoding, the
address, and data (for a write operation) are available on the
80C286 output pins. The 82C288 bus controller decodes the
status signals and generates Multibus compatible read/write
command and local transceiver control signals.
After TS, the perform command (TC) state is entered. Mem-
ory or I/O devices respond to the bus operation during TC,
either transferring read data to the CPU or accepting write
data. TC states may be repeated as often as necessary to
ensure sufficient time for the memory or I/O device to
respond. The READY signal determines whether TC is
repeated. A repeated TC state is called a wait state.
During hold (TH), the 80C286 will float all address, data, and
status output drivers enabling another bus master to use the
local bus. The 80C286 HOLD input signal is used to place
the 80C286 into the TH state. The 80C286 HLDA output sig-
nal indicates that the CPU has entered TH.
Pipelined Addressing
The 80C286 uses a local bus interface with pipelined timing
to allow as much time as possible for data access. Pipelined
timing allows a new bus operation to be initiated every two
processor cycles, while allowing each individual bus opera-
tion to last for three processor cycles.
The timing of the address outputs is pipelined such that the
address of the next bus operation becomes available during
the current bus operation. Or, in other words, the first clock of
the next bus operation is overlapped with the last clock of the
current bus operation. Therefore, address decode and routing
logic can operate in advance of the next bus operation.
External address latches may hold the address stable for the
entire bus operation, and provide additional AC and DC buff-
ering.
The 80C286 does not maintain the address of the current bus
operation during all TC states. Instead, the address for the
next bus operation may be emitted during phase 2 of any TC.
The address remains valid during phase 1 of the first TC to
guarantee hold time, relative to ALE, for the address latch
inputs.
Bus Control Signals
The 82C288 bus controller provides control signals; address
latch enable (ALE), Read/Write commands, data trans-
mit/receive (DT/R), and data enable (DEN) that control the
address latches, data transceivers, write enable, and output
enable for memory and I/O systems.
The Address Latch Enable (ALE) output determines when
the address may be latched. ALE provides at least one sys-
tem CLK period of address hold time from the end of the pre-
vious bus operation until the address for the next bus
operation appears at the latch outputs. This address hold
time is required to support Multibus and common memory
systems.
The data bus transceivers are controlled by 82C288 outputs
Data Enable (DEN) and Data Transmit/Receive (DT/R). DEN
enables the data transceivers; while DT/R controls trans-
ceiver direction. DEN and DT/R are timed to prevent bus
contention between the bus master, data bus transceivers,
and system data bus transceivers.
Command Timing Controls
Two system timing customization options, command extension
and command delay, are provided on the 80C286 local bus.
Command extension allows additional time for external
devices to respond to a command and is analogous to
inserting wait states on the 80C86. External logic can control
the duration of any bus operation such that the operation is
only as long as necessary. The READY input signal can
extend any bus operation for as long as necessary.
Command delay allows an increase of address or write data
setup time to system bus command active for any bus oper-
ation by delaying when the system bus command becomes
active. Command delay is controlled by the 82C288 CMDLY
input. After TS, the bus controller samples CMDLY at each
failing edge of CLK. If CMDLY is HIGH, the 82C288 will not
activate the command signal. When CMDLY is LOW, the
82C288 will activate the command signal. After the com-
mand becomes active, the CMDLY input is not sampled.
When a command is delayed, the available response time
from command active to return read data or accept write
data is less. To customize system bus timing, an address
decoder can determine which bus operations require delay-
ing the command. The CMDLY input does not affect the tim-
ing of ALE, DEN or DT/R.
Figure 23 illustrates four uses of CMDLY. Example 1 shows
delaying the read command two system CLKs for cycle N-1
and no delay for cycle N, and example 2 shows delaying the
read command one system CLK for cycle N-1 and one sys-
tem CLK delay for cycle N.
HLDA
NEW CYCLE
NEW CYCLE
HLDA
READY
NEW CYCLE
READY
HLDA
NEW CYCLE
HOLD
TH
IDLE
TI
COMMAND
TC
STATUS
TS
HLDA
NEW CYCLE
ALWAYS
RESET
READY
NEW CYCLE
FIGURE 21. 80C286 BUS STATES
80C286
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