參數(shù)資料
型號(hào)： CS80C286-12
廠商： Intersil
文件頁(yè)數(shù)： 47/60頁(yè)
文件大小： 0K
描述： IC CPU 16BIT 5V 12.5MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 126
處理器類型： 80C286 16-位
速度： 12.5MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC（24.23x24.23）
包裝： 管件
51
80C286 Instruction Set Summary
Instruction Timing Notes
The instruction clock counts listed below establish the maxi-
mum execution rate of the 80C286. With no delays in bus
cycles, the actual clock count of an 80C286 program will
average 5% more than the calculated clock count, due to
instruction sequences which execute faster than they can be
fetched from memory.
To calculate elapsed times for instruction sequences, multi-
ply the sum of all instruction clock counts, as listed in the
table below, by the processor clock period. An 12.5MHz pro-
cessor clock has a clock period of 80 nanoseconds and
requires an 80C286 system clock (CLK input) of 25MHz.
Instruction Clock Count Assumptions
1. The instruction has been perfected, decoded and is
ready for execution. Control transfer instruction clock
counts include all time required to fetch, decode, and
prepare the next instruction for execution.
2. Bus cycles do not require wait states.
3. There are no processor extension data transfer or local
bus HOLD requests.
4. No exceptions occur during instruction execution.
Instruction Set Summary Notes
Addressing displacements selected by the MOD field are not
shown. If necessary they appear after the instruction fields
shown.
Above/below refers to unsigned value.
Greater refers to more positive signed values.
Less refers to less positive (more negative) signed values
if d = 1, then “to” register; if d = 0 then “from” register
if w = 1, then word instruction; if w = 0, then byte instruction
if s = 0, then 16-bit immediate data form the operand
if s = 1, then an immediate data byte is sign-extended to
form the 16-bit operand
x don’t care
z used for string primitives for comparison with ZF FLAG
If two clock counts are given, the smaller refers to a register
operand and the larger refers to a memory operand
* = add one clock if offset calculation requires summing 3
elements
n = number of times repeated
m = number of bytes of code in next instruction
Level (L) - Lexical nesting level of the procedure
The following comments describe possible exceptions, side
effects and allowed usage for instructions in both operating
modes of the 80C286.
FIGURE 40A. SHORT OPCODE FORMAT EXAMPLE
FIGURE 40B. LONG OPCODE FORMAT EXAMPLE
FIGURE 40. 80C286 INSTRUCTION FORMAT EXAMPLES
Waveforms (Continued)
LOW DISP/DATA
HIGH DISP/DATA
LOW DATA
HIGH DATA
OPCODE
MOD
REG
R/M
dw
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
765 43210 7654 3210
REGISTER OPERAND REGISTERS TO USE IN OFFSET CALCULATION
REGISTER OPERAND/EXTENSION OF OPCODE
REGISTER MODE/MEMORY MODE WITH DISPLACEMENT LENGTH
WORD/BYTE OPERATION
DIRECTION IS TO REGISTER DIRECTION IS FROM REGISTER
OPERATION (INSTRUCTION) CODE
LOW DISP
HIGH DISP
BYTE 5
BYTE 4
BYTE 3
BYTE 2
BYTE 1
LONG OPCODE
MOD
REG
R/M
7654321 07654321 07654321 0
80C286
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