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參數(shù)資料
| 型號(hào)： | CY28346ZXC-2 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 15/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFF OUT CK408 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 35 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
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CY28346-2
........................ Document #: 38-07509 Rev. *B Page 5 of 19
Byte 3: PCIF Clock and 48M Control Register (all bits are read and write functional)
Bit
@Pup
Name
Description
7
1
48M_DOT
48M_DOT Output Control,1 = enabled, 0 = forced LOW
6
1
48M_USB
48M_USB Output Control,1 = enabled, 0 = forced LOW
5
0
PCIF2
PCI_STP#, control of PCIF2.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
4
0
PCIF1
PCI_STP#, control of PCIF1.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
3
0
PCIF0
PCI_STP#, control of PCIF0.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
2
1
PCIF2
PCIF2 Output Control. 1=running, 0=forced LOW
1
PCIF1
PCIF1 Output Control. 1= running, 0=forced LOW
0
1
PCIF0
PCIF0 Output Control. 1= running, 0=forced LOW
Byte 4: DRCG Control Register(all bits are read and write functional)
Bit
@Pup
Name
Description
7
0
SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread)
60
Reserved
5
1
3V66_0
3V66_0 Output Enabled. 1 = enabled, 0 = disabled
4
1
3V66_1/VCH
3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled
3
1
3V66_5
3V66_5 Output Enable. 1 = enabled, 0 = disabled
2
1
66B2/3V66_4
66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled
1
66B1/3V66_3
66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled
0
1
66B0/3V66_2
66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled
Byte 5: Clock Control Register (all bits are read and write functional)
Bit
@Pup
Name
Description
7
0
SS1 Spread Spectrum control bit
6
1
SS0 Spread Spectrum control bit
5
0
66IN to 66M delay Control MSB
4
0
66IN to 66M delay Control LSB
30
Reserved
2
0
48M_DOT edge rate control. When set to 1, the edge is slowed by 15%.
10
Reserved
0
USB edge rate control. When set to 1, the edge is slowed by 15%
Byte 6: Silicon Signature Register[2] (all bits are read-only)
Bit
@Pup
Name
Description
70
60
50
41
3
0
Vendor Code, 011 = IMI
20
11
01
Note:
2. When writing to this register the device will acknowledge the write operation, but the data itself will be ignored.
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參數(shù)描述 |
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| CY28346ZXC-2T | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28346ZXCT | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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| CY28347OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
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