參數(shù)資料
型號: CY28346ZXC-2
廠商: Silicon Laboratories Inc
文件頁數(shù): 8/19頁
文件大?。?/td> 0K
描述: IC CLOCK DIFF OUT CK408 56TSSOP
標(biāo)準(zhǔn)包裝: 35
類型: *
PLL:
輸入: 晶體
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:21
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
CY28346-2
...................... Document #: 38-07509 Rev. *B Page 16 of 19
Tskew
Unbuffered
3V66 to 3V66 Clock
Skew
500
ps
Tskew
Buffered
3V66 to 3V66 Clock
Skew
250
ps
Tccj
DRCG Cycle to
Cycle Jitter
250
ps
66B
Tdc
66B(0:2) Duty Cycle
45
55
45
55
45
55
45
55
%
Tr / Tf
66B(0:2) Rise and
Fall Times
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
ns
Tskew
Any 66B to Any 66B
Skew
175
ps
Tpd
66IN to 66B(0:2)
Propagation Delay
2.5
4.5
2.5
4.5
2.5
4.5
2.5
4.5
ns
Tccj
66B(0:2) Cycle to
Cycle Jitter
100
ps
PCI
Tdc
PCIF(0:2) PCI (0:6)
Duty Cycle
45
55
45
55
45
55
45
55
%
Tperiod
PCIF(0:2) PCI (0:6)
period
30.0
30
nS
Thigh
PCIF(0:2) PCI (0:6)
high time
12.0
nS
Tlow
PCIF(0:2) PCI (0:6)
low time
12.0
nS
Tr/Tf
PCIF(0:2) PCI (0:6)
rise and fall times
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
nS
Tskew
Any PCI clock to
Any PCI clock Skew
500
pS
Tccj
PCIF(0:2) PCI (0:6)
Cycle to Cycle Jitter
250
ps
48M_USB
Tdc
48M_USB Duty
Cycle
45
55
45
55
45
55
45
55
%
Tperiod
48M_USB Period
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333
ns
Tr/Tf
48M_USB Rise and
Fall Times
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.10
ns
Tccj
48M_USB Cycle to
Cycle Jitter
350
ps
48M_DOT
Tdc
48M_DOT Duty
Cycle
45
55
45
55
45
55
45
55
%
Tperiod
48M_DOT Period
20.837
ns
Tr/Tf
48M_DOT Rise and
Fall Times
0.5
1.0
0.5
1.0
0.5
1.0
0.5
1.0
ns
Tccj
48M_DOT Cycle to
Cycle Jitter
350
ps
Note:
22. This figure is additive to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500-ps jitter figure is specified.
AC Parameters (VDD = VDDA = 3.3V ±5%) (continued)
Parameter
Description
66 MHz
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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