參數(shù)資料
型號(hào): CY28346ZXC-2
廠商: Silicon Laboratories Inc
文件頁數(shù): 3/19頁
文件大?。?/td> 0K
描述: IC CLOCK DIFF OUT CK408 56TSSOP
標(biāo)準(zhǔn)包裝: 35
類型: *
PLL:
輸入: 晶體
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:21
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
CY28346-2
...................... Document #: 38-07509 Rev. *B Page 11 of 19
Iout is selectable depending on implementation. The param-
eters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviation from the expected output current is ±7% as shown in
the current accuracy table.
PCI_STP#
PCIF
PCI
setup
t
Figure 7. PCI_STP# Deassertion Waveforms
Figure 8. VTT_PWRGD# Timing Diagram
VID
SEL
VTT_PWRGD#
PWRGD
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_PWRGD#
Sample Sels
Off
On
State 1
Device is not affected,
VTT_PWRGD# is ignored.
VTT_PWRGD# = Low
Delay
>0.25mS
S1
Power Off
S0
VDDA = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for <1.8ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDD3.3= off
Figure 9. Clock Generator Power-up/Run State Program
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