參數資料
型號: CY28346ZXC-2
廠商: Silicon Laboratories Inc
文件頁數: 5/19頁
文件大小: 0K
描述: IC CLOCK DIFF OUT CK408 56TSSOP
標準包裝: 35
類型: *
PLL:
輸入: 晶體
輸出: 時鐘
電路數: 1
比率 - 輸入:輸出: 1:21
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: *
封裝/外殼: *
供應商設備封裝: *
包裝: *
CY28346-2
...................... Document #: 38-07509 Rev. *B Page 13 of 19
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristics:
1. Output impedance of the current mode buffer circuit – Ro
(see Figure 14).
2. Minimum and maximum required voltage operation range
of the circuit – Vop (see Figure 14).
3. Series resistance in the buffer circuit – Ros (see Figure 14).
4. Current accuracy at given configuration into nominal test
load for given configuration.
66B
PCI
PCIF
1.5-
3.5ns
Figure 12. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
PCI
PCIF
Tpci
3V66
Figure 13. Unbuffered Mode – 3V66(0:5) to PCI (0:6) and PCIF(0:2) Phase Relationship
1.2V
0V
Iout
Ros
Ro
VDD3 (3.3V +/- 5%)
Vout = 1.2V max
Vout
Slope ~ 1/R
0
Figure 14.
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