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參數(shù)資料
| 型號： | CY28346ZXC-2 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFF OUT CK408 56TSSOP |
| 標準包裝： | 35 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
CY28346-2
...................... Document #: 38-07509 Rev. *B Page 12 of 19
USB and DOT 48M Phase Relationship
The 48M_USB and 48M_DOT clocks are in phase. It is under-
stood that the difference in edge rate will introduce some in
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See Figure 10.
66IN to 66B Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown in Figure 11.
The Tpd is the prop delay from the input pin (66IN) to the
output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The
measurement is taken at 1.5V.
66B to PCI Buffered Clock Skew
shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to PCI Unbuffered Clock Skew
shows the timing relationship between 3V66(0:5)
and PCI(0:6) and PCIF when configured to run in the unbuf-
fered mode.
Table 7. Host Clock (HCSL) Buffer Characteristics
Characteristic
Minimum
Maximum
Ro
3000 Ohms (recommended)
N/A
Ros
Vout
N/A
1.2V
Table 8. CPU Clock Current Select Function
Mult0
Board Target Trace/Term Z
Reference R, Iref – Vdd (3*Rr)
Output Current
Voh @ Z
0
50 Ohms
Rr = 221 1%, Iref = 5.00 mA
Ioh = 4*Iref
1.0V @ 50
1
50 Ohms
Rr = 475 1%, Iref = 2.32 mA
Ioh = 6*Iref
0.7V @ 50
Table 9. Group Timing Relationship and Tolerances
Description
Offset
Tolerance
Conditions
3V66 to PCI
2.5 ns
1.0 ns
3V66 Leads PCI (unbuffered mode)
48M_USB to 48M_DOT Skew
0.0 ns
1.0 ns
0 degrees phase shift
66B to PCI offset
2.5 ns
1.0 ns
66B leads PCI (buffered mode)
Table 10.Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
PCI Clocks
30
pF
3V66
30
pF
66B
30
pF
48M_USB Clock
20
pF
48M_DOT
10
pF
REF Clock
50
pF
48MUSB
48MDOT
Figure 10. 48M_USB and 48M_DOT Phase Relationship
66IN
66B
Tpd
Figure 11. 66IN to 66B(0:2) Output Delay Figure
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