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參數(shù)資料
| 型號： | CY28346ZXC-2 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFF OUT CK408 56TSSOP |
| 標準包裝： | 35 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
CY28346-2
...................... Document #: 38-07509 Rev. *B Page 10 of 19
Three-state Control of CPU Clocks Clarification
During CPU_STP# and PD# modes, CPU clock outputs may
be set to driven or undriven (three-state) by setting the corre-
sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tsetup). (See
Figure 2.) The PCIF (0:2) clocks will not be affected by this pin
if their control bits in the SMBus register are set to allow them
to be free running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Note that the PCI STOP function is controlled by two inputs.
One is the device PCI_STP# pin number 34 and the other is
SMBus byte 0 bit 3. These two inputs to the function are
logically ANDed. If either the external pin or the internal
SMBus register bit is set low then the stoppable PCI clocks will
be stopped in a logic low state. Reading SMBus Byte 0 Bit 3
will return a 0 value if either of these control bits are set LOW
thereby indicating the devices stoppable PCI clocks are not
running.
Table 6. Cypress Clock Power Management Truth Table
B0b6
B1b6
PD#
CPU_STP# Stoppable CPUT
Stoppable
CPUC
Non-Stop CPUT
Non-Stop CPUC
0
1
Running
0
1
0
Iref x6
Running
0
1
Iref x2
Low
Iref x2
Low
0
Iref x2
Low
Iref x2
Low
0
1
Running
0
1
0
Hi Z
Running
0
1
0
1
Hi Z
0
1
0
Hi Z
1
0
1
Running
1
0
1
0
Iref x6
Running
1
0
1
Hi Z
1
0
Hi Z
1
Running
1
0
Hi Z
Running
1
0
1
Hi Z
1
0
Hi Z
PCI_ST P#
P C IF 33M
PCI 33M
setup
t
Figure 6. PCI_STP# Assertion Waveforms
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