參數(shù)資料
型號(hào)： CY7C1512JV18-267BZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 4M X 18 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 1/26頁(yè)
文件大小： 648K
代理商： CY7C1512JV18-267BZXC
72-Mbit QDR-II SRAM 2-Word
Burst Architecture
CY7C1510JV18, CY7C1525JV18
CY7C1512JV18, CY7C1514JV18
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 001-14435 Rev. *F
Revised July 31, 2009
Features
■ Separate Independent Read and Write Data Ports
Supports concurrent transactions
■ 267 MHz Clock for High Bandwidth
■ 2-word Burst on all Accesses
■ Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 534 MHz) at 267 MHz
■ Two Input Clocks (K and K) for Precise DDR Timing
SRAM uses rising edges only
■ Two Input Clocks for Output Data (C and C) to Minimize Clock
Skew and Flight Time Mismatches
■ Echo Clocks (CQ and CQ) Simplify Data Capture in High Speed
Systems
■ Single Multiplexed Address Input Bus Latches Address Inputs
for both Read and Write Ports
■ Separate Port Selects for Depth Expansion
■ Synchronous Internally Self-timed Writes
■ QDR-II Operates with 1.5 Cycle Read Latency when Delay
Lock Loop (DLL) is enabled
■ Operates like a QDR-I Device with 1 Cycle Read Latency in
DLL Off Mode
■ Available in x8, x9, x18, and x36 Configurations
■ Full Data Coherency, providing most current data
■ Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD
■ Available in 165-Ball FBGA Package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ Variable Drive HSTL Output Buffers
■ JTAG 1149.1 Compatible Test Access Port
■ Delay Lock Loop (DLL) for Accurate Data Placement
Configurations
CY7C1510JV18 – 8M x 8
CY7C1525JV18 – 8M x 9
CY7C1512JV18 – 4M x 18
CY7C1514JV18 – 2M x 36
Functional Description
The CY7C1510JV18, CY7C1525JV18, CY7C1512JV18, and
CY7C1514JV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR-II architecture has
separate data inputs and data outputs to eliminate the need to
‘turnaround’ the data bus that exists with common I/O devices.
Access to each port is through a common address bus.
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II read
and write ports are completely independent of one another. To
maximize data throughput, both read and write ports are
equipped with DDR interfaces. Each address location is
associated with two 8-bit words (CY7C1510JV18), 9-bit words
(CY7C1525JV18), 18-bit words (CY7C1512JV18), or 36-bit
words (CY7C1514JV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of both input clocks (K and K and C and C),
memory bandwidth is maximized while simplifying system
design by eliminating bus ‘turnarounds’.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
267 MHz
250 MHz
Unit
Maximum Operating Frequency
267
250
MHz
Maximum Operating Current
x8
1375
1245
mA
x9
1385
1255
x18
1495
1365
x36
1710
1580
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1512KV18-200BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4Mb x 18 200 MHz RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1512KV18-200BZXI 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C1512KV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (4Mx18) 1.8v 250MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1512KV18-250BZCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4Mx18 72MB 2.9V RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1512KV18-250BZI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (4Mx18) 1.8v 250MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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