參數(shù)資料
型號(hào)： CY7C1347D-250BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 128K X 36 CACHE SRAM, 2.4 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
文件頁(yè)數(shù)： 1/21頁(yè)
文件大?。?/td> 2790K
代理商： CY7C1347D-250BGC
128K x 36 Synchronous-Pipelined Cache SRAM
CY7C1347D
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-05022 Rev. *E
Revised November 11, 2004
Features
Fast access times: 2.5 and 3.5 ns
Fast clock speed: 250, 225, 200, and 166 MHz
1.5-ns set-up time and 0.5-ns hold time
Fast OE access times: 2.5 ns and 3.5 ns
Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V –5% and +10% power supply
3.3V or 2.5V I/O supply
5V tolerant inputs except I/Os
Clamp diodes to VSS at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Three chip enables for depth expansion and address
pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down for portable applications
JTAG boundary scan
JEDEC standard pinout
Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
This Cypress Synchronous Burst SRAM employs high-speed,
low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells
with advanced synchronous peripheral circuitry and a 2-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE), depth-expansion Chip Enables (CE2 and CE2), Burst
Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa,
BWb, BWc, BWd, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written.
Four pins are used to implement JTAG test capabilities: Test
Mode Select (TMS), Test Data-in (TDI), Test Clock (TCK), and
Test Data-out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation.
The CY7C1347D operates from a +3.3V power supply. All
inputs and outputs are LVTTL-compatible
Selection Guide
CY7C1347D-250
CY7C1347D-225
CY7C1347D-200
CY7C1347D-166
Maximum Access Time (ns)
2.5
3.5
Maximum Operating Current (mA)
450
400
360
300
Maximum CMOS Standby Current (mA)
10
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