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參數(shù)資料
| 型號(hào)： | CY7C1217H |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1-Mbit (32K x 36) Flow-Through Sync SRAM |
| 中文描述： | 1兆位（32K的× 36）流量通過(guò)同步SRAM的 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 362K |
| 代理商： | CY7C1217H |
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CY7C1217H
Document #: 38-05670 Rev. *B
Page 6 of 16
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ Active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
Truth Table [2, 3, 4, 5, 6]
Cycle Description
Address
Used
CE1 CE2 CE3 ZZ ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Deselected Cycle,
Power-down
None
H
X
L
X
L
X
L-H
Tri-State
Deselected Cycle,
Power-down
None
L
X
L
X
L-H
Tri-State
Deselected Cycle,
Power-down
None
L
X
H
L
X
L-H
Tri-State
Deselected Cycle,
Power-down
None
L
X
L
H
L
X
L-H
Tri-State
Deselected Cycle,
Power-down
None
X
L
H
L
X
L-H
Tri-State
Sleep Mode, Power-down
None
X
H
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
X
H
L-H
Tri-State
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
X
L
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
L
H
L
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
L
H
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
L
X
H
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
L
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
L
H
L-H
Tri-State
Read Cycle, Suspend Burst
Current
H
X
L
X
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
L
X
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
L
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
L
X
H
L
X
L-H
D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
[+] Feedback
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