參數(shù)資料
型號: CY7C1217H
廠商: Cypress Semiconductor Corp.
英文描述: 1-Mbit (32K x 36) Flow-Through Sync SRAM
中文描述: 1兆位(32K的× 36)流量通過同步SRAM的
文件頁數(shù): 5/16頁
文件大?。?/td> 362K
代理商: CY7C1217H
CY7C1217H
Document #: 38-05670 Rev. *B
Page 13 of 16
Read/Write Timing[16, 18, 19]
Notes:
18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
19. GW is HIGH.
Timing Diagrams (continued)
tCYC
t
CL
CLK
tADH
tADS
ADDRESS
t
CH
tAH
tAS
A2
tCEH
tCES
Single WRITE
D(A3)
A3
A4
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
t
WEH
t
WES
t
OEHZ
tDH
tDS
tCDV
tOELZ
A1
A5
A6
D(A5)
D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
ADSP
ADSC
BWE, BW[A:D]
CE
ADV
OE
Data In (D)
Data Out (Q)
[+] Feedback
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