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參數(shù)資料
| 型號： | CY7C2566KV18-450BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 8M X 8 DDR SRAM, 0.37 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 831K |
| 代理商： | CY7C2566KV18-450BZI |
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PRELIMINARY
CY7C2566KV18, CY7C2577KV18
CY7C2568KV18, CY7C2570KV18
Document Number: 001-15889 Rev. *D
Page 7 of 28
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR-II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR-II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off
Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 K
Ω or less pull up resistor. The device behaves in DDR-I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with DDR-I timing.
TDO
Output
TDO for JTAG.
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
Input
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
Input
Not Connected to the Die. Can be tied to any voltage level.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VSS
Ground
Ground for the Device.
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
Table 2. Pin Definitions (continued)
Pin Name
IO
Pin Description
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| CY7C25682KV18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C25682KV18-400BZXC | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C25682KV18-450BZC | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 1.8v 450MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C25682KV18-500BZC | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 1.8v 500MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C25682KV18-550BZXC | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 2.9v 550MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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