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參數(shù)資料
| 型號(hào)： | CY7C2566KV18-450BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 8M X 8 DDR SRAM, 0.37 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 831K |
| 代理商： | CY7C2566KV18-450BZI |
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PRELIMINARY
CY7C2566KV18, CY7C2577KV18
CY7C2568KV18, CY7C2570KV18
Document Number: 001-15889 Rev. *D
Page 9 of 28
Echo Clocks
Echo clocks are provided on the DDR-II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free-running clocks and are
synchronized to the input clock of the DDR-II+. The timing for the
echo clocks is shown in the Switching Characteristics on page
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
On-Die Termination (ODT)
These devices have an On-Die Termination feature for Data
inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K
and K). The termination resistors are integrated within the chip.
The ODT range selection is enabled through ball R6 (ODT pin).
The ODT termination tracks value of RQ where RQ is the resistor
tied to the ZQ pin. ODT range selection is made during power up
initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175
Ω < RQ < 350Ω (where RQ is the resistor tied to
ZQ pin)
. A HIGH on this pin selects a high range that follows
RQ/1.66 for 175
Ω < RQ < 250Ω (where RQ is the resistor tied to
ZQ pin). When left floating, a high range termination value is
selected by default. For a detailed description on the ODT imple-
mentation, refer to the application note, On-Die Termination for
QDRII+/DDRII+ SRAMs.
PLL
These chips use a PLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the PLL is locked after 20
μs
of stable clock. The PLL can also be reset by slowing or stopping
the input clock K and K for a minimum of 30 ns. However, it is
not necessary to reset the PLL to lock to the desired frequency.
The PLL automatically locks 20
μs after a stable clock is
presented. The PLL may be disabled by applying ground to the
DOFF pin. When the PLL is turned off, the device behaves in
DDR-I mode (with one cycle latency and a longer access time).
For information, refer to the application note, PLL Considerations
in QDRII/DDRII/QDRII+/DDRII+.
Application Example
Figure 1 shows two DDR-II+ used in an application.
Figure 1. Application Example
DQ
A
SRAM#2
LD
CQ/CQ
K
ZQ
K
ODT
R/W BWS
BUS
MASTER
(CPU or ASIC)
DQ
Addresses
LD
R/W
R = 250ohms
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
ODT
R = 250ohms
BWS
DQ
A
SRAM#1
LD
K
ZQ
CQ/CQ
K
ODT
R/W BWS
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