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| 型號： | CYDD18S72V18-167BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 256K X 72 DUAL-PORT SRAM, 9 ns, PBGA484 |
| 封裝： | 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 1/53頁 |
| 文件大小： | 2422K |
| 代理商： | CYDD18S72V18-167BGI |
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FullFlex Synchronous
DDR Dual-Port SRAM
FullFlex
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-06072 Rev. *I
Revised December 21, 2006
Features
True dual-ported memory allows simultaneous access
to the shared array from each port
Synchronous pipelined operation with selectable
Double Data Rate (DDR) or Single Data Rate (SDR)
operation on each port
— DDR interface at 200 MHz
— SDR interface at 250 MHz
— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)
Selectable pipelined or flow-through mode
1.5V or 1.8V core power supply
Commercial and Industrial temperature ranges
IEEE 1149.1 JTAG boundary scan
Available in 484-ball PBGA Packages and 256-ball
FBGA Packages
FullFlex72 family
— 18 Mbit: 256K x 36 x 2 DDR or 256K x 72 SDR
(CYDD18S72V18)
— 9 Mbit: 128K x 36 x 2 DDR or 128K x 72 SDR
(CYDD09S72V18)
— 4 Mbit: 64K x 36 x 2 DDR or 64 x 72 SDR
(CYDD04S72V18)
FullFlex36 family
— 36 Mbit: 512K x 36 x 2 DDR (CYDD36S36V18)
— 18 Mbit: 256K x 36 x 2 DDR (CYDD18S36V18)
— 9 Mbit: 128K x 36 x 2 DDR (CYDD09S36V18)
— 4 Mbit: 64K x 36 x 2 DDR (CYDD04S36V18)
FullFlex18 family
— 36 Mbit: 1M x 18 x 2 DDR (CYDD36S18V18)
— 18 Mbit: 512K x 18 x 2 DDR (CYDD18S18V18)
— 9 Mbit: 256K x 18 x 2 DDR (CYDD09S18V18)
— 4 Mbit: 128K x 18 x 2 DDR (CYDD04S18V18)
Built-in deterministic access control to manage
address collisions
— Deterministic flag output upon collision detection
— Collision detection on back-to-back clock cycles
— First Busy Address readback
Advanced features for improved high-speed data
transfer and flexibility
— Variable Impedance Matching (VIM)
— Echo clocks
— Selectable LVTTL (3.3V), Extended HSTL
(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on
each port
— Burst counters for sequential memory access
— Mailbox with interrupt flags for message passing
— Dual Chip Enables for easy depth expansion
Functional Description
The FullFlex
Dual-Port SRAM families consist of 4-Mbit,
9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static
RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two
ports are provided, allowing the array to be accessed simulta-
neously. Simultaneous access to a location triggers determin-
istic access control. For FullFlex72, these ports can operate
independently in DDR mode with 36-bit bus widths or in SDR
mode with 72-bit bus widths. For FullFlex36 and FullFlex18,
the ports operate in DDR mode only. Each port can be
independently configured for two pipelined stages for SDR
mode or 2.5 stages in DDR mode. Each port can also be
configured to operate in pipelined or flow-through mode in
SDR mode.
Advanced features include built-in deterministic access
control to manage address collisions during simultaneous
access to the same memory location, Variable Impedance
Matching (VIM) to improve data transmission by matching the
output driver impedance to the line impedance, and echo
clocks to improve data transfer.
To reduce the static power consumption, chip enables can be
used to power down the internal circuitry. The number of
cycles of latency before a change in CE0 or CE1 will enable
or disable the databus matches the number of cycles of read
latency selected for the device. In order for a valid write or read
to occur, both chip enable inputs on a port must be active.
Each port contains an optional burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally.
Additional features of this device include a mask register and
a mirror register to control counter increments and
wrap-around. The counter-interrupt (CNTINT) flags notify the
host that the counter will reach maximum count value on the
next clock cycle. The host can read the burst-counter internal
address, mask register address, and busy address on the
address lines. The host can also load the counter with the
address stored in the mirror register by utilizing the retransmit
functionality. Mailbox interrupt flags can be used for message
passing, and JTAG boundary scan and asynchronous Master
Reset (MRST) are also available. The logic block diagram in
Figure 1 displays these features.
The FullFlex72 DDR family of devices is offered in a 484-ball
plastic BGA package. The FullFlex36 and FullFlex18 DDR
only families of devices are offered in both 484-ball and
256-ball fine pitch BGA packages.
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