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參數(shù)資料
| 型號(hào)： | CYDD18S72V18-167BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 256K X 72 DUAL-PORT SRAM, 9 ns, PBGA484 |
| 封裝： | 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 48/53頁 |
| 文件大?。?/td> | 2422K |
| 代理商： | CYDD18S72V18-167BGI |
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FullFlex
Document #: 38-06072 Rev. *I
Page 52 of 53
Document History Page
Document Title: FullFlex Synchronous DDR Dual-Port SRAM
Document Number: 38-06072
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
274729
See ECN
SPN
New data sheet
*A
294239
See ECN
SPN
Updated VIM section
Added notes 7
Added timing for 100 MHz with DLL Disabled
Removed tPS
*B
301331
See ECN
SPN
Added note 19
Updates Selectable I/O Standard Section
*C
318834
See ECN
SPN
Updated Block Diagram
Updated 484 pinouts, changed pins D11, W12, K3, K20
Added note 4 - Leaving pin DNU disables VIM
Updated 256 pinout, changed pins C10, G5, N7, N10
Added note 18, 19, 20, 21
Updated parameters in table 16
Updated note 1
*D
386692
See ECN
SPN
Updated ordering information
Added statement about no echo clocks for flow-through mode
Updated electrical characteristics
Added note 27 (timing for x18 devices)
Updated address readback latency to 2 cycles for DDR mode
Updated DDR timing numbers for tCD, tDC, tCCQ, tCQHQV, tCQHQX, tCKHZ, tCKLZ
Updated input edge rate
Removed -133 speed bin electrical characteristics and timing columns
Updated Table 5 on collision detection to be the same as the one found in the EROS
Added description of busy readback in collision detection section
Changed dummy write descriptions
Updated PORTSTD[1:0] connection details
Updated ZQ pins connection details
Updated address count notes
Updated note 17, BO to BEO
Added power supply requirements to MRST and VC_SEL
Updated 484 ball package
Changed name from FLEX72-E, FLEX36-E, AND FLEX18-E to FullFlex72,
FullFlex36, and FullFlex18
*E
401662
See ECN
KGH
Updated READY description to include Wired OR note
Updated master reset to include wired OR note for READY
Updated electrical characteristics to include IOH and IOL values
Updated electrical characteristics to include READY
Added IIX3
Updated maximum input capacitance
Added note 29
Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1
Changed voltage name from VDDQ to VDDIO
Changed voltage name from VDD to VCORE
Updated the Package Type for the CYDXXS36V18 parts
Updated the Package Type for the CYDXXS18V18 parts
Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256
Included an OE Controlled Write for Flow-through Mode Switching Waveform
Included a Read with Echo Clock Switching Waveform
Included a Unit column for Table 5
Removed Switching Characteristic tCA from chart
Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode
Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow-through Mode
Updated AC Test Load and Waveforms
Included FullFlex36 DDR 484-ball BGA Pinout (Top View)
Included FullFlex18 DDR 484-ball BGA Pinout (Top View) Included Timing
Parameter tCORDY
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| CYDD18S72V18-200BBC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 256KX72 0.5NS 484BGA - Bulk |
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