參數(shù)資料
型號(hào)： CYDD18S72V18-167BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 256K X 72 DUAL-PORT SRAM, 9 ns, PBGA484
封裝： 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484
文件頁(yè)數(shù)： 52/53頁(yè)
文件大?。?/td> 2422K
代理商： CYDD18S72V18-167BGI
FullFlex
Document #: 38-06072 Rev. *I
Page 8 of 53
Pin Definitions
Left Port
Right Port
Description
A[19:0]L
A[19:0]R
Address Inputs.[1]
DQ[71:0]L
DQ[71:0]R
Data Bus Input/Output.[2]
BE[7:0]L
BE[7:0]R
Byte Select Inputs.[3] Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
BUSYL
BUSYR
Port Busy Output. When there is an address match and both chip enables are active for
both ports, an external BUSY signal is asserted on the fifth clock cycle from when the collision
occurs.
C/CL
C/CR
Clock Signal.[18] Maximum clock input rate is fMAX. Tie C to VSS when operating in SDR
mode.
CE0L
CE0R
Active LOW Chip Enable Input.
CE1L
CE1R
Active HIGH Chip Enable Input.
CQENL
CQENR
Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port.
CQ0L
CQ0R
Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Echo Clock Signal Output
for DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for FullFlex18
devices.
CQ0L
CQ0R
Inverted Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Inverted Echo
Clock Signal Output for DQ[17:0] for FullFlex36 devices. Inverted Echo Clock Signal Output
for DQ[8:0] for FullFlex18 devices.
CQ1L
CQ1R
Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Echo Clock Signal
Output for DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9] for
FullFlex18 devices.
CQ1L
CQ1R
Inverted Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Inverted Echo
Clock Signal Output for DQ[35:18] for FullFlex36 devices. Inverted Echo Clock Signal Output
for DQ[17:9] forFullFlex18 devices.
DDRONL[17]
DDRONR[17]
DDR Enable Input. Assert HIGH to enable DDR clocking on respective port.
ZQ[1:0]L
ZQ[1:0]R
VIM Output Impedance Matching Input. To use, connect a calibrating resistor between ZQ
and ground. The resistor must be five times larger than the intended line impedance driven
by the dual-port. Assert HIGH or leave DNU to disable Variable Impedance Matching.
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
LowSPDL
LowSPDR
Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation at less
than 100 MHz, assert this pin LOW.
PORTSTD[1:0]L
PORTSTD[1:0]R
Port Clock/Address/Control/Data/Echo Clock/I/O Standard Select Input. Assert these
pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS, and
HIGH/HIGH for 1.8V LVCMOS, respectively. These pins must be driven by VTTL referenced
levels.
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to Write to, or HIGH to Read from the
dual-port memory array.
READYL
READYR
Port DLL Ready Output. This signal will be asserted LOW when the DLL and Variable
Impedance Matching circuits have completed calibration. This is a wired OR capable output.
CNT/MSKL
CNT/MSKR
Port Counter/Mask Select Input. Counter control input.
ADSL
ADSR
Port Counter Address Load Strobe Input. Counter control input.
CNTENL
CNTENR
Port Counter Enable Input. Counter control input.
Notes:
17. DDRONL and DDRONR needs to tie to the same voltage level for FullFlex36 and FullFlex18 Family.
18. C and C are complimentary for DDR operation.
19. PORTSTD[1:0]L and PORTSTD[1:0]R have internal pull-down resistors.
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