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參數(shù)資料
| 型號： | CYDD18S72V18-167BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 256K X 72 DUAL-PORT SRAM, 9 ns, PBGA484 |
| 封裝： | 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 53/53頁 |
| 文件大?。?/td> | 2422K |
| 代理商： | CYDD18S72V18-167BGI |
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FullFlex
Document #: 38-06072 Rev. *I
Page 9 of 53
Selectable I/O Standard
The FullFlex device families also offer the option of choosing
one of four port standards for the device. Each port can
independently select standards from single-ended HSTL class
I, single-ended LVTTL, 2.5V LVCMOS, or 1.8V LVCMOS. The
selection of the standard is determined by the PORTSTD pins
for each port. These pins must be connected to a VTTL power
supply. This will determine the input clock, address, control,
data, and Echo clock standard for each port as shown in
Table 2. Please note that only 1.8V LVCMOS and HSTL are
supported for 4-Mbit, 9-Mbit, 18-Mbit devices running at
250MHz SDR, and for 36-Mbit devices running at 200 MHz
SDR.
Clocking
Separate clocks synchronize the operations on each port.
Each port has two clock inputs C and C. In SDR mode only the
C input clock is used and C should be tied to VSS. In this
mode, all the transactions on the address, control, and data
will be on the C rising edge. In DDR mode, both C and C will
be used and these signals are complementary. In this mode,
all transactions on the address and control, except for the byte
enables, will occur on the C rising edge. Transactions on the
data input, output, and byte enables will be on the C and C
rising edges.
Double Data Rate (DDR)
In DDR mode with a x36 bus width, the input data is sampled
on both edges of the input clock. During a write, on the rising
edge of C, the first 36 bits (DQ[71:36]) will be latched into a
register. On the rising edge of C, the next 36 bits (DQ[35:0])
will be latched into a register. During a read, the first 36 bits
are driven out first on the rising edge of C. The next 36 bits will
be driven out on the rising edge of C. The internal bus width of
the FullFlex72 family is still x72. All counter operation is based
upon the x72 word width. The DDR option is set on a per port
basis by the configuration of the DDRON pin. Table 3 shows
the data assignment for SDR and DDR configuration. The
column on the right (Data Pin Name) shows the pins on which
data is presented on the data lines.
CNTRSTL
CNTRSTR
Port Counter Reset Input. Counter control input.
CNTINTL
CNTINTR
Port Counter Interrupt Output. This pin is asserted LOW one cycle before the unmasked
portion of the counter is incremented to all “1s”.
WRPL
WRPR
Port Counter Wrap Input. When the burst counter reaches the maximum count, on the next
counter increment WRP can be set LOW to load the unmasked counter bits to 0 or set HIGH
to load the counter with the value stored in the mirror register.
RETL
RETR
Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for
repeated access to the same segment of memory.
VREFL
VREFR
Port External HSTL I/O Reference Input. This pin is left DNU when HSTL is not used.
VDDIOL
VDDIOR
Port Data I/O Power Supply.
FTSELL
FTSELR
Port Flow-through Mode Select Input. Assert this pin LOW to select Flow-through mode.
Assert this pin HIGH to select Pipelined mode. Selection for SDR only.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation
is required at power-up. This pin must be driven by VDDIOL referenced levels.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V LVCMOS.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
Operation for LVTTL or 2.5V LVCMOS.
TRST
JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS.
TCK
JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL
or 2.5V LVCMOS.
VSS
Ground Inputs.
VCORE
Device Core Power Supply.
VTTL
LVTTL Power Supply.
Pin Definitions (continued)
Left Port
Right Port
Description
Table 2. Port Standard Selection
PORTSTD1
PORTSTD0
I/O Standard
VSS
LVTTL
VSS
VTTL
HSTL
VTTL
VSS
2.5V LVCMOS
VTTL
1.8V LVCMOS
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