參數(shù)資料
型號: DAC1208D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 19/98頁
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
19 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
The worst case clock skew is given by
δ
t
2
= PH03
PH01.
The minimum allowable trace delay for the MDS signal is given by
Δ
t =
δ
t
2
.
In real applications, the master DAC can be anywhere and both conditions must be
satisfied:
δ
t
2
<
Δ
t
mds
< TDAC
δ
t
1
.
Example:
clock generator skew =
±
80 ps
FR4 substrate
15 cm/ns delay
clock trace length difference = 3 cm and 4 cm
Output sampling rate = 650 Msps
200 ps + 80 ps <
Δ
t
mds
< 1538 ps
(266 ps + 80 ps)
280 ps <
Δ
t
mds
< 1192 ps
4.2 cm < L
mds
< 17.8 cm
Fig 10. Clock skew case 2: Master is closest
001aal071
ref clock
TDAC
master clock
PH01
slave 1 clock
PH02
slave 2 clock
PH03
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