參數(shù)資料
型號: DAC1208D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 42/98頁
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
42 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
Table 24.
Bit
7 to 0
FREQNCO_MSB register (address 06h) bit description
Symbol
FREQ_NCO[31:24]
Access
R/W
Value
26h
Description
most significant 8 bits for the NCO frequency setting
Table 25.
Bit
7 to 0
PHINCO_LSB register (address 07h) bit description
Symbol
PH_NCO[7:0]
Access
R/W
Value
00h
Description
lower 8 bits for the NCO phase setting
Table 26.
Bit
7 to 0
PHINCO_MSB register (address 08h) bit description
Symbol
PH_NCO[15:8]
Access
R/W
Value
00h
Description
most significant 8 bits for the NCO phase setting
Table 27.
Default settings are shown highlighted.
Bit
Symbol
7
DAC_A_PD
DAC_A_CFG_1 register (address 09h) bit description
Access
R/W
Value
Description
DAC A power
on
off
DAC A Sleep mode
disabled
enabled
lower 6 bits for the DAC A offset
0
1
6
DAC_A_SLEEP
R/W
0
1
00h
5 to 0
DAC_A_OFFSET[5:0]
R/W
Table 28.
Bit
7 to 6
DAC_A_CFG_2 register (address 0Ah) bit description
Symbol
DAC_A_GAIN_COARSE[1:0]
Access
R/W
Value
1h
Description
least significant 2 bits for the DAC A gain setting for
coarse adjustment
the 6 bits for the DAC A gain setting for fine
adjustment
5 to 0
DAC_A_GAIN_FINE[5:0]
R/W
00h
Table 29.
Bit
7 to 6
DAC_A_CFG_3 register (address 0Bh) bit description
Symbol
DAC_A_GAIN_COARSE[3:2]
Access
R/W
Value
3h
Description
most significant 2 bits for the DAC A gain setting for
coarse adjustment
most significant 6 bits for the DAC A offset
5 to 0
DAC_A_OFFSET[11:6]
R/W
00h
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