參數(shù)資料
型號(hào)： DAC1208D650HN
廠商： NXP SEMICONDUCTORS
元件分類： DAC
英文描述： Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述： 12-BIT DAC, PQCC64
封裝： 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁(yè)數(shù)： 53/98頁(yè)
文件大?。?/td> 557K
代理商： DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
53 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
Table 62.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
RST_EXT_FCLK_TIME[7:0]
RST_EXT_FCLK register (address 04h) bit description
Access
R/W
Value
3Fh
Description
specifies extension time reset_fclk in f
clk
periods
Table 63.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
RST_EXT_DCLK_TIME[7:0]
RST_EXT_DCLK register (address 05h) bit description
Access
R/W
Value
20h
Description
specifies extension time reset_dclk (in dclk-periods)
Table 64.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
DCSMU_PREDIVIDER[7:0]
DCSMU_PREDIVCNT register (address 06h) bit description
Access
R/W
Value
1Eh
Description
value used by dcsmu predivider (at f
clk
)
Table 65.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
PLL_CHARGE_TIME[7:0]
PLL_CHARGETIME register (address 07h) bit description
Access
R/W
Value
32h
Description
PLL charge time
(at f
clk
/DCSMU_PREDIVIDER[7:0])
Table 66.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
PLL_RUNIN_TIME[7:0]
PLL_RUN_IN_TIME register (address 08h) bit description
Access
R/W
Value
32h
Description
PLL run in time (at f
clk
/DCSMU_PREDIVIDER[7:0])
Table 67.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
CA_RUNIN_TIME[7:0]
CA_RUN_IN_TIME register (address 09h) bit description
Access
R/W
Value
04h
Description
clock alignment run in time
(at f
clk
/DCSMU_PREDIVIDER[7:0])
Table 68.
Default settings are shown highlighted.
Bit
Symbol
3 to 0
SET_VCM[3:0]
SET_VCM_VOLTAGE register (address 16h) bit description
Access
R/W
Value
02h
Description
set lane common-mode voltage (see
Table 75
)
Table 69.
Default settings are shown highlighted.
Bit
Symbol
6 to 4
SET_SYNC_VCOM[2:0]
SET_SYNC register (address 17h) bit description
Access
R/W
Value
4h
Description
set synchronization transmitter common-mode level
(see
Table 76
)
set synchronization transmitter output level swing
(see
Table 77
)
2 to 0
SET_SYNC_LEVEL[2:0]
R/W
3h
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參數(shù)描述
DAC1208D650HN/C1,5 功能描述:數(shù)模轉(zhuǎn)換器- DAC DL 12BIT DAC 650MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1208D650HN-C1 制造商:Integrated Device Technology Inc 功能描述:HVQFN64 - Bulk
DAC1208D650HN-C18 制造商:Integrated Device Technology Inc 功能描述:HVQFN64 - Tape and Reel
DAC1208D650W1/DB,598 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 DAC DEMOBOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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