參數(shù)資料
型號(hào): DAC1208D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁(yè)數(shù): 63/98頁(yè)
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
63 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
Table 91.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
SEL_RE_INIT[2:0]
SYNCOUT_MODE register (address 0Ch) bit description
Access
R/W
Value
Description
reinitialization mode
i_re_init when 1 of the lane_rst's is active
i_re_init when rst_ln0 or rst_ln1 is active
i_re_init when rst_ln2 or rst_ln3 is active
i_re_init when rst_ln0 is active
i_re_init when rst_ln1 is active
i_re_init when rst_ln2 is active
i_re_init when rst_ln3 is active
i_re_init remains '0'
synchronization polarity
sync_out is active when LOW
sync_out is active when HIGH
synchronization mode
sync when one of the four lane_syncs is active
sync when all four lane_syncs are active
sync when sync_ln0 or sync_ln1 is active
sync when both sync_ln0 and sync_ln1 are active
sync when sync_ln2 or sync_ln3 is active
sync when both sync_ln2 and sync_ln3 are active
sync when sync_ln0 is active
sync when sync_ln1 is active
sync when sync_ln2 is active
sync when sync_ln3 is active
sync remains fixed '1'
sync remains fixed '0'
000
001
010
011
100
101
110
111
4
SYNC_POL
R/W
0
1
3 to 0
SEL_SYNC[3:0]
R/W
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
other
Table 92.
Bit
3
LANE_POLARITY register (address 0Dh) bit description
Symbol
POL_LN3
Access
R/W
Value
Description
lane 3 data polarity
no action
invert all data bits of lane 3
lane 2 data polarity
no action
invert all data bits of lane 2
lane 1 data polarity
no action
invert all data bits of lane 1]
lane 0 data polarity
no action
invert all data bits of lane 0
0
1
2
POL_LN2
R/W
0
1
1
POL_LN1
R/W
0
1
0
POL_LN0
R/W
0
1
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