參數(shù)資料
型號: DAC1208D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 49/98頁
文件大小: 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
49 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
4
MDS_RELOCK
R/W
relock mode
no action
relock when lockout occurs
number of succeeding 'equal'-detections until lock
0
1
Fh
3 to 0
MDS_LOCK_DELAY[3:0]
R/W
Table 54.
Default settings are shown highlighted.
Bit
Symbol
MDS_MISCCNTRL1 register (address 06h) bit description
…continued
Access
Value
Description
Table 55.
Default settings are shown highlighted.
Bit
Symbol
6 to 0
MDS_ADJDELAY[6:0]
MDS_ADJDELAY register (address 08h) bit description
Access
R
Value
-
Description
actual value adjustment delay
Table 56.
Default settings are shown highlighted.
Bit
Symbol
7
EARLY
MDS_STATUS0 register (address 09h) bit description
Access
R
Value
Description
early signal (sampled) from early-late detector
false
true
late signal (sampled) from early-late detector
false
true
0
1
6
LATE
R
0
1
5
EQUAL
R
equal signal (sampled) from early-late detector
false
true
result equal check
false
true
adjustment delay maximum value stops the search
false
true
adjustment delay minimum value stops the search
false
true
evaluation logic has detected equal condition
false
true
evaluation logic active
false
true
0
1
4
MDS_LOCK
R
0
1
3
EARLY_ERROR
R
0
1
2
LATE_ERROR
R
0
1
1
EQUAL_FOUND
R
0
1
0
MDS_ACTIVE
R
0
1
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