參數(shù)資料
型號: DAC1208D650HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝: DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 13/98頁
文件大小: 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
13 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
10.2.1
Lane input
Each lane is CML compliant. It is terminated to a common voltage with an integrated 50
Ω
resistor.
The common-mode voltage is programmable by the SET_VCM_VOLTAGE register as
shown in
Table 75 on page 55
.
DC coupling is only possible if both the DAC and the transmitter have the same
common-mode voltage. If this is not the case AC coupling is required.
The deserializer performs the incoming data clock recovery and also the serial-to-parallel
conversion. Therefore, each lane includes its own PLL that must first lock.
The clock alignment module transfers the data from the regenerated clock to the frame
clock domain. The frequency of both clocks is the same but the phase relationship
between the clocks is unknown.
10.2.2
Sync and word align
As stated in JESD204A, the transmitter and the receiver first have to synchronize. This is
achieved through SYNC_OUT signals and a sync pattern (K28.5 symbol). The receiver
(i.e. DAC1208D650) first drives its SYNC_OUT outputs. The sync pattern is continuously
sent until the receiver deasserts the SYNC_OUT signal.
Fig 4.
Lane input termination
V
tt
001aak166
50
Ω
Ztt
50
Ω
Vin_p
Vin_n
Fig 5.
DC coupling
Fig 6.
AC coupling
001aak162
50
Ω
50
Ω
50
Ω
50
Ω
Zdiff = 100
Ω
data in +
data in
001aak163
50
Ω
50
Ω
50
Ω
50
Ω
Zdiff = 100
Ω
V
DD1
V
DD2
data in +
data in
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