參數(shù)資料
型號： DAC1208D650HN
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝： DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù)： 80/98頁
文件大?。?/td> 557K
代理商： DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
80 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
Table 152. LN0_CFG_8 register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
4 to 0
LN0_N’[4:0]
Access
R
Value
-
Description
number of bits per sample minus 1
Table 153. LN0_CFG_9 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
4 to 0
LN0_S[4:0]
Access
R
Value
-
Description
number of samples per converter per frame cycle
minus 1
Table 154. LN0_CFG_10 register (address 0Ah) bit description
Default settings are shown highlighted.
Bit
Symbol
7
LN0_HD
4 to 0
LN0_CF[4:0]
Access
R
R
Value
-
-
Description
high density
number of control words per frame cycle
Table 155. LN0_CFG_11 register (address 0Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN0_RES1[7:0]
Access
R
Value
-
Description
lane 0 reserved field
Table 156. LN0_CFG_12 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN0_RES2[7:0]
Access
R
Value
-
Description
lane 0 reserved field
Table 157. LN0_CFG_13 register (address 0Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN0_FCHK[7:0]
Access
R
Value
-
Description
lane 0 checksum
Table 158. LN1_CFG_0 register (address 10h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN1_DID[7:0]
Access
R
Value
-
Description
lane 1 device ID
Table 159. LN1_CFG_1 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
3 to 0
LN1_BID[3:0]
Access
R
Value
-
Description
lane 1 bank ID
Table 160. LN1_CFG_2 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
4 to 0
LN1_LID[4:0]
Access
R
Value
-
Description
lane 1 lane ID
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參數(shù)描述
DAC1208D650HN/C1,5 功能描述:數(shù)模轉(zhuǎn)換器- DAC DL 12BIT DAC 650MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1208D650HN-C1 制造商:Integrated Device Technology Inc 功能描述:HVQFN64 - Bulk
DAC1208D650HN-C18 制造商:Integrated Device Technology Inc 功能描述:HVQFN64 - Tape and Reel
DAC1208D650W1/DB,598 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 DAC DEMOBOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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