參數(shù)資料
型號: DAC1208D650HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝: DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 73/98頁
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
73 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
Table 124. INTR_MISC_ENA register (address 0Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
7
INTR_ENA_CS_INIT_LN3
6
INTR_ENA_CS_INIT_LN2
5
INTR_ENA_CS_INIT_LN1
4
INTR_ENA_CS_INIT_LN0
3
INTR_ENA_BUF_ERR_LN3
2
INTR_ENA_BUF_ERR_LN2
1
INTR_ENA_BUF_ERR_LN1
0
INTR_ENA_BUF_ERR_LN0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
0
0
Description
intr_misc in case cs_state_ln3 = cs_init
intr_misc in case cs_state_ln2 = cs_init
intr_misc in case cs_state_ln1 = cs_init
intr_misc in case cs_state_ln0 = cs_init
generate interrupt if ILA_BUF_ERR_LN3 = 1
generate interrupt if ILA_BUF_ERR_LN2 = 1
generate interrupt if ILA_BUF_ERR_LN1 = 1
generate interrupt if ILA_BUF_ERR_LN0 = 1
Table 125. FLAG_CNT_LSB_LN0 register (address 10h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
FLAG_CNT_LN0[7:0]
Access
R
Value
-
Description
LSBs of flag_counter lane 0
Table 126. FLAG_CNT_MSB_LN0 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
FLAG_CNT_LN0[15:8]
Access
R
Value
-
Description
MSBs of flag_counter lane 0
Table 127. FLAG_CNT_LSB_LN1 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
FLAG_CNT_LN1[7:0]
Access
R
Value
-
Description
LSBs of flag_counter lane 1
Table 128. FLAG_CNT_MSB_LN1 register (address 13h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
FLAG_CNT_LN1[15:8]
Access
R
Value
-
Description
MSBs of flag_counter lane 1
Table 129. FLAG_CNT_LSB_LN2 register (address 14h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
FLAG_CNT_LN2[7:0]
Access
R
Value
-
Description
LSBs of flag_counter lane 2
Table 130. FLAG_CNT_MSB_LN2 register (address 15h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
FLAG_CNT_LN2[15:8]
Access
R
Value
-
Description
MSBs of flag_counter lane 2
Table 131. FLAG_CNT_LSB_LN3 register (address 16h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
FLAG_CNT_LN3[7:0]
Access
R
Value
-
Description
LSBs of flag_counter lane 3
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