參數(shù)資料
型號: DAC1208D650HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝: DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 70/98頁
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
70 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
10.15.2.10
Page 5 bit definition detailed description
Please refer to
Table 108
for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 109. ILA_MON_1_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 4
ILA_MON_LN1[3:0]
3 to 0
ILA_MON_LN0[3:0]
Access
R
R
Value
-
-
Description
ila_buf_ln1 pointer
ila_buf_ln0 pointer
Table 110. ILA_MON_3_2 register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 4
ILA_MON_LN3[3:0]
3 to 0
ILA_MON_LN2[3:0]
Access
R
R
Value
-
-
Description
ila_buf_ln3 pointer
ila_buf_ln2 pointer
Table 111. ILA_BUF_ERR register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
3
ILA_BUF_ERR_LN3
Access
R
Value
Description
lane 3 ila buffer error
ila_buf_ln3 pointer is in range
ila_buf_ln3 pointer is out of range
0
1
2
ILA_BUF_ERR_LN2
R
lane 2 ila buffer error
ila_buf_ln2 pointer is in range
ila_buf_ln2 pointer is out of range
lane 1 ila buffer error
ila_buf_ln1 pointer is in range
ila_buf_ln1 pointer is out of range
lane 0 ila buffer error
ila_buf_ln0 pointer is in range
ila_buf_ln0 pointer is out of range
0
1
1
ILA_BUF_ERR_LN1
R
0
1
0
ILA_BUF_ERR_LN0
R
0
1
Table 112. CA_MON register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 6
CA_MON_LN3[1:0]
5 to 4
CA_MON_LN2[1:0]
3 to 2
CA_MON_LN1[1:0]
1 to 0
CA_MON_LN0[1:0]
Access
R
R
R
R
Value
-
-
-
-
Description
clock alignment phase monitor lane 3
clock alignment phase monitor lane 2
clock alignment phase monitor lane 1
clock alignment phase monitor lane 0
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