參數(shù)資料
型號： DAC1208D650HN
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝： DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù)： 58/98頁
文件大小： 557K
代理商： DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
58 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
10.15.2.8
Page 4 bit definition detailed description
Please refer to
Table 78
for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 79.
Default settings are shown highlighted.
Bit
Symbol
7
SR_SWA_LN3
6
SR_SWA_LN2
5
SR_SWA_LN1
4
SR_SWA_LN0
3
SR_CA_LN3
2
SR_CA_LN2
1
SR_CA_LN1
0
SR_CA_LN0
SR_DLP_0 register (address 00h) bit description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
0
0
Description
soft reset sync_word_alignment lane 3
soft reset sync_word_alignment lane 2
soft reset sync_word_alignment lane 1
soft reset sync_word_alignment lane 0
soft reset clock_alignment lane 3
soft reset clock_alignment lane 2
soft reset clock_alignment lane 1
soft reset clock_alignment lane 0
Table 80.
Default settings are shown highlighted.
Bit
Symbol
7
SR_CNTRL_LN3
6
SR_CNTRL_LN2
5
SR_CNTRL_LN1
4
SR_CNTRL_LN0
3
SR_DEC_LN3
2
SR_DEC_LN2
1
SR_DEC_LN1
0
SR_DEC_LN0
SR_DLP_1 register (address 01h) bit description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
0
0
Description
soft reset controller lane 3
soft reset controller lane 2
soft reset controller lane 1
soft reset controller lane 0
soft reset decoder_10b8b lane 3
soft reset decoder_10b8b lane 2
soft reset decoder_10b8b lane 1
soft reset decoder_10b8b lane 0
Table 81.
Default settings are shown highlighted.
Bit
Symbol
7
FORCE_LOCK_LN3
FORCE_LOCK register (address 02h) bit description
Access
R/W
Value
Description
lane 3 lock mode
automatic lock sync_word_alignment lane 3
manual lock sync_word_alignment lane 3
lane 2 lock mode
automatic lock sync_word_alignment lane 2
manual lock sync_word_alignment lane 2
lane 1 lock mode
automatic lock sync_word_alignment lane 1
manual lock sync_word_alignment lane 1
lane 0 lock mode
automatic lock sync_word_alignment lane 0
manual lock sync_word_alignment lane 0
0
1
6
FORCE_LOCK_LN2
R/W
0
1
5
FORCE_LOCK_LN1
R/W
0
1
4
FORCE_LOCK_LN0
R/W
0
1
相關(guān)PDF資料
PDF描述
DAC1208D750HN Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
DAC1208D750HN Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
DL-5538S-C550-SB 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE
DL-5538S-C450-FB 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE
DL-5538S-C450-S 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DAC1208D650HN/C1,5 功能描述:數(shù)模轉(zhuǎn)換器- DAC DL 12BIT DAC 650MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1208D650HN-C1 制造商:Integrated Device Technology Inc 功能描述:HVQFN64 - Bulk
DAC1208D650HN-C18 制造商:Integrated Device Technology Inc 功能描述:HVQFN64 - Tape and Reel
DAC1208D650W1/DB,598 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 DAC DEMOBOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*