參數(shù)資料
型號: DAC1208D650HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝: DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 52/98頁
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
52 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
10.15.2.6
Page 2 bit definition detailed description
Please refer to
Table 59
for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 60.
Default settings are shown highlighted.
Bit
Symbol
5
FULL_RE_INIT
MAINCONTROL register (address 00h) bit description
Access
R/W
Value
Description
initialization
quick reinitialization
full reinitialization
synchronization
synchronization starts with '0'
synchronization starts with '1'
must be written with ’0’
must be written with ’0’
reset_dclk
release reset_dclk
force reset_dclk
reset_fclk
release reset_fclk
force reset_fclk
0
1
4
SYNC_INIT_LEVEL
R/W
0
1
3
2
1
-
-
FORCE_RESET_DCLK
R/W
R/W
R/W
0
1
0
FORCE_RESET_FCLK
R/W
0
1
Table 61.
Default settings are shown highlighted.
Bit
Symbol
7
SR_CDI
JCLK_CNTRL register (address 03h) bit description
Access
R/W
Value
Description
cdi reset
no action
soft reset cdi
cdi mode
cdi_mode 0 (^2 modes)
cdi_mode 1 (^4 modes)
cdi_mode 2 (^8 modes)
reserved
f
clk
polarity
no action
invert polarity
f
clk
clock source
dclk
×
2
dclk
dclk_div2; running
dclk_div2; reset dclk_div2 divider
0
1
5 to 4
CDI_MODE[1:0]
R/W
00
01
10
11
2
FCLK_POL
R/W
0
1
1 to 0
FCLK_SEL[1:0]
R/W
00
01
10
11
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