參數(shù)資料
型號(hào)： DM9161A
廠商： Electronic Theatre Controls, Inc.
英文描述： 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述： 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁(yè)數(shù)： 22/45頁(yè)
文件大小： 1206K
代理商： DM9161A
Preliminary
22
Version: DM9161A-DS-P04
Jan.19, 2005
7.2.11 Power Reduced Mode
The Signal detect circuit is always turned on to monitor whether there is any signal on the media. In case of cable
disconnection,, DM9161A will automatically turn off the power and enter the Power Reduced mode, regardless of its operation
mode being N-way auto-negotiation or forced mode. While in the Power Reduced mode, the transmit circuit will continue
sending out fast link pulse with minimum power consumption. If a valid signal is detected from the media, which might be N-way
fast link pulse, 10Base-T normal link pules, or 100Base-TX MLT3 signals, the device wakes up and resumes normal operation
mode.
Automatic reduced power down mode can be disabled by writing Zero to Reg.16.4.
7.2.12 Power Down Mode
Power Down mode is entered by setting Reg.0.11 to ONE or pulling PWRDWN pin high, which disables all transmit and
receive functions, and MII interface functions except the MDC/MDIO management interface.
7.2.13 Reduced Transmit Power Mode
Additional transmit power reduction can be gained by designing with 1.25:1 turns ration magnetic on its TX side and using a
8.5K
resistor on BGRES and BGRESG pins, and the TX+/TX- pulled high resistors being changed from 50 to 78
configuration could reduce about 20% of transmit power.
7.3 Auto MDIX Functional Description
The DM9161A supports the automatic detect cable connection type, MDI/MDIX (straight through/cross over). A
manual configuration by register bit for MDI or MDIX is still accepted.
When set to automatic, the polarity of MDI/MDIX controlled timing is generated by a 16-bits LFSR. The switching cycle time is
located from 200ms to 420ms. The polarity control is always switch until detect received signal. After selected MDI or MDIX, the
polarity status can be read by register bit (20.7).(See page33,8.12 specified config register-20 bit 7)7.3.1 Function Setting.
Pin 39 is used to enable Auto MDIX function.
Pull pin 39 low will enable it, and pull pin 39 high will disable it.
Specified config Register 20 bit 4 (20, 4) is used by programmer to disable Auto MDIX function. Write register 20 bit
4 to
“
1
“
will disable Auto MDIX function. Its default value is
“
0
“
. When the register 20 bit 4 (20, 4) is set to
“
1
“
, the register 20
bit 5(20, 5) is used to select straight through or cross over mode,
“
0
“
is for straight through, and
“
1
“
is for cross over.
RX + /- from DM9161A RX+/- to RJ45
. This
TX + /- from DM9161A TX+/- to RJ45
* MDI : __________
* MDIX : - - - - - - - - -
This feature is able to detect the required cable connection type.( straight through or crossed over ) and make correction
automatically
8. MII Register Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9161A_09 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DM9161AE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
DM9161AEP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DM9161B 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DM9161BEP 制造商:DAVICOM 功能描述:IC TRX 10/100MBPS ENET PHY48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3 / 802.3u; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:48; Interface Type:MII; Operating Temperature ;RoHS Compliant: Yes
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