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參數(shù)資料
| 型號(hào)： | DM9161A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 39/45頁 |
| 文件大小： | 1206K |
| 代理商： | DM9161A |
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39
Preliminary
Version: DM9161A-DS-P04
Jan.19,2005
9.4.6 100BASE-TX Transmit Timing Parameters
Symbol
t
TXc
t
TXh
, t
TXl
t
TXs
t
TXh
t
TXOD
t
1
t
2
t
TXpd
t
TXr/f
Parameter
Min.
39.998
16
12
0
-
-
-
3
Typ.
40
20
-
-
4
4
8
4
Max.
40.002
24
-
-
25
-
-
-
5
Unit
ns
ns
ns
ns
ns
BT
BT
BT
ns
Conditions
50ppm
90% To 10%, Into
100ohm Differential
TXCLK Cycle Time
TXCLK High/Low Time
TXD [0:3], TXEN, TXER Setup To TXCLK High
TXD [0:3], TXEN, TXER Hold From TXCLK High
TXCLK to Output Delay
TXEN Sampled To CRS Asserted
TXEN Sampled To CRS De-asserted
TXEN Sampled To TX+/- Out (Tx Latency)
100TX Driver Rise/Fall Time
Note 1. Typical values are at 25
and are for design aid only; not guaranteed and not subject to production testing.
9.4.7 100BASE-TX Transmit Timing Diagram
TXCLK
t
TX
h
t
2
t
TX
S
t
1
t
TX
pd
t
TX
r/f
TXD [0:3],
TXEN, TXER
CRS
100TX+/-
tTXc
tTXh
tTXOD
9.4.8 100BASE-TX Receive Timing Parameters
Symbol
t
RXc
T
RXh,
t
RXl
t
RXs
t
RXh
t
RXpd
t
1
t
2
t
3
t
4
t
5
1. Typical values are at 25
Parameter
Min.
39.998
16
10
10
-
-
-
10
14
14
Typ.
40
20
Max.
40.002
24
-
-
-
-
-
14
18
18
Unit
Conditions
50ppm
RXCLK Cycle Time
RXCLK High/Low Time
RXD [0:3], RXDV, RXER Setup To RXCLK High
RXD [0:3], RXDV, RXER Hold From RXCLK High
RX+/- In To RXD [0:3] Out (Rx Latency)
CRS Asserted To RXD [0:3], RXDV, RXER
CRS De-asserted To RXD [0:3], RXDV, RXER
RX+/- In To CRS Asserted
RX+/- Quiet To CRS De-asserted
RX+/- In To COL De-Asserted
and are for design aid only; not guaranteed and not subject to production testing.
-
-
ns
ns
BT
BT
BT
BT
BT
BT
15
4
0
-
-
-
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