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參數(shù)資料
| 型號： | DM9161A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 8/45頁 |
| 文件大?。?/td> | 1206K |
| 代理商： | DM9161A |
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Preliminary
8
Version: DM9161A-DS-P04
Jan.19, 2005
5.2 Media Interface, 4 pins
Pin No.
3,4
7,8
Pin Name
RX+
RX-
TX+
TX-
I/O
I
Description
Differential Receive Pair
Differential data is received from the media
O Differential Transmit Pair/PECL Transmit Pair
Differential data is transmitted to the media in TP mode
5.3 LED Interface, 3 pins
Pin No.
11
Pin Name
LED0
/OP0
I/O
O,
LI
(U)
Description
LED Driver output 0
OP0: (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9161A according to the Table A. The value is latched into the
DM9161A registers at power-up/reset
LED Driver output 1
OP1: (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9161A according to the Table A. The value is latched into the
DM9161A registers at power-up/reset
LED Driver output 2
OP2: (power up reset latch input)
This pin is used to control the forced or advertised operating mode of the
DM9161A according to the Table A. The value is latched into the
DM9161A registers at power-up/reset
12
LED1
/OP1
O,
LI
(U)
13
LED2
/OP2
O,
LI
(U)
5.4 Mode, 3 pins
Pin No.
10
Pin Name
PWRDWN
I/O
I
Description
Power Down Control
Asserted high to force the DM9161A into power down mode. When in
power down mode, most of the DM9161A circuit block’s power is turned
off, only the MII management interface (MDC, MDIO) logic is available
(the PHY should respond to management transactions and should not
generate spurious signals on the MII)). To leave power down mode, the
DM9161A needs the hardware or software reset with the PWRDWN pin
low
Cable Status or Link Status
This pin is used to indicate the status of the cable connection when
power up reset latch low (Default)
0 = Without cable connection
1 = With cable connection
This pin is used to indicate the status of the Link connection when power
up reset latch high
0 = With link
1 = Without link
Auto MDIX Control
1: Disable auto mode
0: Enable auto MDI/MDIX mode
14
CABLESTS
/LINKSTS
O,
LI
(D)
39
DISMDIX
I
(D)
5.5 Bias and Clock, 4 pins
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9161A_09 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9161AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| DM9161AEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9161B | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9161BEP | 制造商:DAVICOM 功能描述:IC TRX 10/100MBPS ENET PHY48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3 / 802.3u; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:48; Interface Type:MII; Operating Temperature ;RoHS Compliant: Yes |
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