參數(shù)資料
型號: DM9161A
廠商: Electronic Theatre Controls, Inc.
英文描述: 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述: 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁數(shù): 41/45頁
文件大?。?/td> 1206K
代理商: DM9161A
41
Preliminary
Version: DM9161A-DS-P04
Jan.19,2005
9.4.12 MII 10BASE-T Receive Nibble Timing Parameters
Symbol
t
RXs
RXD [0:3], RXDV, RXER Setup To RXCLK High
t
RXh
RXD [0:3], RXDV, RXER Hold From RXCLK High
t
RXpd
RX+/- To RXD [0:3] Out (Rx Latency)
t
1
CRS Asserted To RXD [0:3], RXDV, RXER,Asserted
t
2
CRS De-asserted To RXD [0:3], RXDV,
RXER,De-asserted
t
3
RXI In To CRS Asserted
t
4
RXI Quiet To CRS De-asserted
9.4.13 MII 10BASE-T Receive Nibble Timing Diagram
Parameter
Min.
5
5
-
1
-
Typ.
-
-
7
14
-
Max.
-
-
-
20
3
Unit
ns
ns
BT
BT
BT
Conditions
1
1
2
10
4
15
BT
BT
RXCLK
t
2
t
1
t
TX
pd
RXD [0:3],
RXDV, RXER
CRS
RX+/-
t
RX
S
t
RX
h
t
4
t
3
9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters
Symbol
Parameter
t
1
Clock/Data Pulse Width
t
2
Clock Pulse To Data Pulse Period
t
3
Clock Pulse To Clock Pulse Period
t
4
FLP Burst Width
t
5
FLP Burst To FLP Burst Period
-
Clock/Data Pulses in a Burst
9.4.15 Auto-negotiation and Fast Link Pulse Timing Diagram
Min.
-
55.5
111
-
8
17
Typ.
100
62.5
125
2
-
-
Max.
-
69.5
139
-
24
33
Unit
ns
us
us
ms
ms
pulse
Conditions
DATA = 1
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