參數(shù)資料
型號(hào)： DM9801E
廠商： Electronic Theatre Controls, Inc.
英文描述： 1M home Phonrline Network Physical Layer Single Chip Transceiver
中文描述： 100萬(wàn)家庭Phonrline網(wǎng)絡(luò)物理層單芯片收發(fā)器
文件頁(yè)數(shù)： 23/61頁(yè)
文件大小： 589K
代理商： DM9801E
DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Preliminary
Version: DM9801-DS-P02
March 20, 2000
23
MII Serial Management Register Map (INTFSEL = 0, MII Mode)
Register
Address
0
BMCR
Register Name
Access
Type
RW
Default
Value
0x0000
Description
Basic Mode Control Register (valid only when MII
Emulation Support is enabled, Config1 = 1).
Basic Mode Status Register (valid only when MII
Emulation Support is enabled, Config1 = 1).
PHY Identifier Register #1 (valid only when MII Emulation
Support is enabled, Config1 = 1).
PHY Identifier Register #2 (valid only when MII Emulation
Support is enabled, Config1 = 1).
Auto-negotiation Advertisement Register (valid only when
MII Emulation Support is enabled, Config1 = 1).
Auto-negotiation Link Partner Ability Register (valid only
when MII Emulation Support is enabled, Config1 = 1).
Auto-Negotiation Expansion Register (valid only when MII
Emulation Support is enabled, Config1 = 1).
Reserved
Control Register
Status Register
Interrupt Mask Register
Interrupt Status Register
Transmit PHY Communication Hi Word
Transmit PHY Communication Lo Word
Receive PHY Communication Hi Word
Receive PHY Communication Lo Word
Peak Level and Noise Level Register
Noise Ceiling and Noise Floor Register
Noise Events and Noise Attack Register
Four Wire Enable and Disable Link Register
AID Address Register
AID Interval and AID ISBI Register
DATA ISBI Control Register
Transmit Pulse Control Register
1
BMSR
RO
0x0820
2
PHYIDR1
RO
0x0181
3
PHYIDR2
RO
0xB900
4
ANAR
RO
0x0021
5
ANLPAR
RO
0x0000
6
ANER
RO
0x0000
7-15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Not Used
CNTRL
STATUS
IMASK
ISTAT
TX_PCOM_HI
TX_PCOM_LO
RX_PCOM_HI
RX_PCOM_LO
PEAK_NOISE
NOISE_CNTRL_A
NOISE_CNTRL_B
FWENA
AID_ADDRESS
AID_CNTRL
SYM_CNTRL
TX_SIG_CNTRL
Tri-State
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x0005
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0xFF04
0x8007
0x00F4
0x0000
0x0000
0x4014
0x1C2C
0x4404
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
(PIN#)
Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
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