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參數(shù)資料
| 型號(hào)： | DM9801E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M home Phonrline Network Physical Layer Single Chip Transceiver |
| 中文描述： | 100萬家庭Phonrline網(wǎng)絡(luò)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 41/61頁 |
| 文件大?。?/td> | 589K |
| 代理商： | DM9801E |
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DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Preliminary
Version: DM9801-DS-P02
March 20, 2000
41
Noise Floor Register - Register 18 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
18.7 -
18.0
Noise Ceiling Register - Register 19 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
19.7 -
19.0
Noise Attack Register - Register 20 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
20.7 -
20.0
Default
0x07, RW
Description
NSE_FLOOR
Noise Floor:
The minimum value of the NOISE_LEVEL measurement.
Default
0x80, RW
Description
NSE_CEILING
Noise Ceiling:
The maximum value of the NOISE_LEVEL measurement.
Default
0xF4, RW
Description
NSE_ATTACK
Noise Attack:
Sets the attack characteristics of the noise algorithm. The high nibble
sets the number of noise events needed to raise the NOISE_LEVEL
immediately, while the low nibble is the number of noise events needed
to raise the NOISE_LEVEL at the end of an 870 msec period.
Noise Events Register - Register 21 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
21.7 -
21.0
Default
0x00, RW
Description
NSE_EVENTS
Noise Events:
An 8 bit counter that records the number of noise events detected.
Overflows are held as 0xFF. This register is cleared by setting bit 6 of
the Control register (CLR_NS_EVNT).
Four Wire Enable Register - Register 22 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
22.7 -
22.2
22.1
DIS_LNK
Default
0, RW
Description
Reserved
Reserved
These bits will always be read as 0.
Disable Link:
This bit disables link integrity feature.
Four Wire Enable:
When read this bit will indicate the status of FWENA (pin 57) as read
during power up. If the FWENA pin status is 1 on power up, this bit can
be written to change the FWENA status. If the FWENA pin status is 0,
on power up, writes to this bit are ignored.
0, RW
22.0
FWENA
0, RW
Aid Address Register - Register 25 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
25.7 -
25.0
Default
0x00, RW
Description
AID_ADDRESS
AID Address:
Unless bit 7 of the Control register is set, the DM9801 is assured to
select a unique AID Address.
Addresses above 0xEF are reserved. Address 0xFF is defined to
indicate a Remote Command.
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