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參數(shù)資料
| 型號： | DM9801E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M home Phonrline Network Physical Layer Single Chip Transceiver |
| 中文描述： | 100萬家庭Phonrline網(wǎng)絡(luò)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 38/61頁 |
| 文件大小： | 589K |
| 代理商： | DM9801E |
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DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
38
Preliminary
Version: DM9801-DS-P02
March 20, 2000
IMASKB (Interrupt Mask B) Register - Register 5 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
5.7 – 5.2
Software
Interrupts
Description
0,RW
Software Interrupts:
1= Software interrupts will not activate the INT# pin
0= Software interrupts will activate the INT# pin
Mask RXPCOM Valid:
1= RX_PCOM_VAL will not activate the INT# pin
0= RX_PCOM_VAL will activate the INT# pin
Mask TXPCOM Ready:
1= TX_PCOM_RDY will not activate the INT# pin
0= TX_PCOM_RDY will activate the INT# pin
5.1
MSK_RX_PCOM
0,RW
5.0
MSK_TX_PCOM
0,RW
ISTAT (Interrupt Status A) Register - Register 6 (INTFSEL = 1, GPSI Mode)
This register reports the state of each interrupt source regardless of the state of the IMASK Register.
Bit
Bit Name
Default
6.7 – 6.4
Reserved
0,RW
Description
Reserved:
Write as 0, ignore on read
Packet Received:
When set this bit indicates a packet has been received
Packet Transmitted:
When set this bit indicates a packet has been transmitted
Remote Command Received:
When set this bit indicates a valid remote command has been
received.
Remote Command Sent:
When set this bit indicates a valid remote command has been
sent.
6.3
PKT_RCVD
0,RW
6.2
PKT_XMITD
0,RW
6.1
RMT_CMD_RCV
0,RW
6.0
RMT_CMD_SNT
0,RW
ISTAT (Interrupt Status B) Register - Register 7 (INTFSEL = 1, GPSI Mode)
This register reports the state of each interrupt source regardless of the state of the IMASK Register.
Bit
Bit Name
Default
7.7 – 7.2
Software
Interrupts
Description
0,RW
Software Interrupts:
When set any bit of those registers indicates software interrupt
is on.
RXPCOM Valid:
When set this bit indicates a non-null RX_PCOM has been
received.
Accessing the high byte of the RX_PCOM register clears this
bit.
TXPCOM Ready:
When set this bit indicates a non-null TX_PCOM has been
loaded into the TX_PCOM register.
7.1
RX_PCOM_VAL
0,RW
7.0
TX_PCOM_RDY
0,RW
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