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參數(shù)資料
| 型號： | DM9801E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1M home Phonrline Network Physical Layer Single Chip Transceiver |
| 中文描述： | 100萬家庭Phonrline網(wǎng)絡物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 4/61頁 |
| 文件大?。?/td> | 589K |
| 代理商： | DM9801E |
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DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
4
Preliminary
Version: DM9801-DS-P02
March 20, 2000
Pin Description
Pin No.
Station Interface: Receive Data, Transmit Data and Management
85
or
STXDAT
Transmit data input pin for serial data from the GPSI.
84
or
BP1
Most significant bit of a 2-bit encoded select. The BP1 and BP0 inputs, select
one of four, 64-byte, SPROM pages to initialize the DM9801 management
registers. Master mode must be selected using the SMODE input.
83
or
SI
This is the serial data input pin to the DM9801 for the SPI bus. The SPI bus
operation is only valid if GPSI mode is selected.
82
or
SMODE
This input pin selects the SPI buses mode of operation. The SPI bus modes
of operation are:
Master Mode (SMODE = 0)
Slave Mode (SMODE = 1)
The SPI bus operation is only valid if GPSI mode is selected.
86
or
STDCLK
mode.
Serial Transmit Data Clock (GPSI Mode, INTFSEL = 1):
STDCLK is an output from the DM9801. Used as the transmit reference clock
to clock in the STXDATA when in GPSI interface mode.
81
or
STXEN
Serial Transmit Enable (GPSI Mode, INTFSEL = 1):
Used to enable the transmit function of the GPSI when in GPSI interface
mode.
66
or
BP0
maximum clock rate is 2.5MHz.
SPROM Boot Page Select 0 (GPSI Mode, INTFSEL = 1):
Least significant bit of a 2-bit encoded select. The BP1 and BP0 inputs,
select one of four, 64-byte, SPROM pages to initialize the DM9801
management registers. Master mode must be selected using the SMODE
input.
Pin Name
I/O
Description
TXD0
I
Transmit Data Bit 0 (MII Mode, INTFSEL = 0):
Transmit data input pin, bit 0, for nibble data from the MII
Serial Transmit Data Bit (GPSI Mode, INTFSEL = 1):
TXD1
I
Transmit Data Bit 1 (MII Mode, INTFSEL = 0):
Transmit data input pin, bit 1, for nibble data from the MII
SPROM Boot Page Select 1 (GPSI Mode, INTFSEL = 1):
TXD2
I
Transmit Data Bit 2 (MII Mode, INTFSEL = 0):
Transmit data input pin, bit 2, for nibble data from the MII
Serial Data Input (GPSI Mode, INTFSEL = 1):
TXD3
I
Transmit Data Bit 3 (MII Mode, INTFSEL = 0):
Transmit data input pin, bit 3, for nibble data from the MII
Serial Mode Select (GPSI Mode, INTFSEL = 1):
TX_CLK
O,Z
MII Transmit Clock (MII Mode, INTFSEL = 0):
TX_CLK is an output pin from the DM9801. Used as the transmit data
reference clock, to clock in nibble data from the MII when in MII interface
TX_EN
I
MII Transmit Enable (MII Mode, INTFSEL = 0):
MII Transmit enable input, used to enable the transmit function of the MII
when in MII interface mode.
MDC
I
MII Serial Management Clock (MII Mode, INTFSEL = 0):
Synchronous clock to the MDIO management data input/output serial
interface which is asynchronous to transmit and receive clocks. The
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