參數(shù)資料
型號(hào): DM9801E
廠商: Electronic Theatre Controls, Inc.
英文描述: 1M home Phonrline Network Physical Layer Single Chip Transceiver
中文描述: 100萬(wàn)家庭Phonrline網(wǎng)絡(luò)物理層單芯片收發(fā)器
文件頁(yè)數(shù): 57/61頁(yè)
文件大?。?/td> 589K
代理商: DM9801E
DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Preliminary
Version: DM9801-DS-P02
March 20, 2000
57
SPI Master Mode Timing Diagram
SCLK
SO
SCS#
SI
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5
Data Byte 0
TDLYscs
l
TDLYsov
TWIDTHclk
h
TWIDTHclk
l
TSETsi
v
Instruction Byte
Address Byte
b7
b6
SPI Master Timing Parameters
Symbol
TWIDTHclkh
TWIDTHclkl
TDLYscsl
TDLYsov
TSETsiv
SPI Slave Mode Timing Diagram
Parameter
Min.
790
790
40
20
Typ.
Max.
810
810
40
60
Unit
ns
ns
ns
ns
ns
Conditions
Positive half-cycle pulse width
Negative half-cycle pulse width
Falling clock edge to SCS# low
Falling clock edge to SO valid
SI valid to rising clock edge
SCLK
SI
SCS#
SO
TSETscsl
TSETsiv
TWIDTHclk
h
TWIDTHclkl
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5
Instruction Byte
Address Byte
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5
(High-Z when writing)
Data Byte
TDLYsov
TDLYsoz
TSETscsh
Data Byte
(Don't care on read)
SPI Master Timing Parameters
Symbol
TWIDTHclkh
TWIDTHclkl
TSETscsl
TSETscsh
TDLYsov
TDLYsoz
TSETsiv
Parameter
Min.
400
400
50
50
50
Typ.
Max.
50
100
Unit
ns
ns
ns
ns
ns
ns
ns
Conditions
Positive half-cycle pulse width
Negative half-cycle pulse width
SCS# low to rising clock edge
SCS# high to rising edge clock
Falling edge clock to SO valid
Falling edge clock to SO tri-state
SI valid to rising clock edge
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