參數(shù)資料
型號(hào)： DP83848C-MAU-EK
廠商： National Semiconductor
文件頁(yè)數(shù)： 24/86頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION DP83848C
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)
已用 IC / 零件： DP83848C
已供物品： 板
相關(guān)產(chǎn)品： DP83848CVVX/NOPBTR-ND - TXRX ETHERNET PHYTER 48-LQFP
DP83848CVV-ND - IC TXRX ETHERNET PHYTER 48-LQFP
29
www.national.com
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4.2.2.2 Base Line Wander Compensation
The DP83848C is completely ANSI TP-PMD compliant and
includes Base Line Wander (BLW) compensation. The
BLW compensation block can successfully recover the TP-
PMD defined “killer” pattern.
BLW can generally be defined as the change in the aver-
age DC content, relatively short period over time, of an AC
coupled digital transmission over a given transmission
medium. (i.e., copper wire).
BLW results from the interaction between the low fre-
quency components of a transmitted bit stream and the fre-
quency response of the AC coupling component(s) within
the transmission system. If the low frequency content of
the digital bit stream goes below the low frequency pole of
the AC coupling transformers then the droop characteris-
tics of the transformers will dominate resulting in potentially
serious BLW.
The digital oscilloscope plot provided in Figure 9 illustrates
the severity of the BLW event that can theoretically be gen-
erated during 100BASE-TX packet transmission. This
event consists of approximately 800 mV of DC offset for a
period of 120
s. Left uncompensated, events such as this
can cause packet loss.
4.2.3 Signal Detect
The signal detect function of the DP83848C is incorporated
to meet the specifications mandated by the ANSI FDDI TP-
PMD Standard as well as the IEEE 802.3 100BASE-TX
Standard for both voltage thresholds and timing parame-
ters.
Note that the reception of normal 10BASE-T link pulses
and fast link pulses per IEEE 802.3u Auto-Negotiation by
the 100BASE-TX receiver do not cause the DP83848C to
assert signal detect.
4.2.4 MLT-3 to NRZI Decoder
The DP83848C decodes the MLT-3 information from the
Digital Adaptive Equalizer block to binary NRZI data.
4.2.5 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is
required in order to present NRZ formatted data to the
descrambler.
4.2.6 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.
Figure 9. 100BASE-TX BLW Event
相關(guān)PDF資料
PDF描述
2-5492591-0 CA 50/125UMRIS SCDUP/2.5BAY 20M1
6278899-1 CA,62.5,MTRJ-SC
L-07W18NKV4T WIREWOUND INDUCTOR 18NH 0402
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DP83848C-POE-EK 功能描述:以太網(wǎng)開發(fā)工具 DP83848 POE CARD COMM TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
DP83848CVV 制造商:Texas Instruments 功能描述:IC, 10/100 ETHERNET PHY, SMD, LQFP48
DP83848CVV/NOPB 功能描述:以太網(wǎng) IC PHYTER COMMERCIAL TEMP SGL PORT RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
DP83848CVV/NOPB 制造商:Texas Instruments 功能描述:Ethernet Transceiver
DP83848CVVX 制造商:Texas Instruments 功能描述:PHY 1-CH 10Mbps/100Mbps 48-Pin LQFP T/R
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