參數(shù)資料
型號: DP83848C-MAU-EK
廠商: National Semiconductor
文件頁數(shù): 7/86頁
文件大?。?/td> 0K
描述: BOARD EVALUATION DP83848C
標準包裝: 1
主要目的: 接口,以太網(wǎng)
已用 IC / 零件: DP83848C
已供物品:
相關(guān)產(chǎn)品: DP83848CVVX/NOPBTR-ND - TXRX ETHERNET PHYTER 48-LQFP
DP83848CVV-ND - IC TXRX ETHERNET PHYTER 48-LQFP
www.national.com
14
DP
83
84
8C
1.7 10 Mb/s and 100 Mb/s PMD Interface
1.8 Special Connections
1.9 Power Supply Pins
Signal Name
Type
Pin #
Description
TD-, TD+
I/O
16, 17
Differential common driver transmit output (PMD Output Pair).
These differential outputs are automatically configured to either
10BASE-T or 100BASE-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Re-
ceive Input pair.
These pins require 3.3V bias for operation.
RD-, RD+
I/O
13, 14
Differential receive input (PMD Input Pair). These differential in-
puts are automatically configured to accept either 100BASE-TX
or 10BASE-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the
Transmit Output pair.
These pins require 3.3V bias for operation.
Signal Name
Type
Pin #
Description
RBIAS
I
24
Bias Resistor Connection. A 4.87 k
1% resistor should be con-
nected from RBIAS to GND.
PFBOUT
O
23
Power Feedback Output. Parallel caps, 10
F (Tantalum pre-
ferred) and 0.1
F, should be placed close to the PFBOUT. Con-
nect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See
Section 5.4 for proper placement pin.
PFBIN1
PFBIN2
I
18
37
Power Feedback Input. These pins are fed with power from
PFBOUT pin. A small capacitor of 0.1
F should be connected
close to each pin.
Note: Do not supply power to these pins other than from
PFBOUT.
RESERVED
I/O
8, 9, 10, 11,
12
RESERVED: These pins must be left unconnected.
RESERVED
I/O
20, 21
RESERVED: These pins must be pulled-up through 2.2 k
resis-
tors to AVDD33 supply.
Signal Name
Pin #
Description
IOVDD33
32, 48
I/O 3.3V Supply
IOGND
35, 47
I/O Ground
DGND
36
Digital Ground
AVDD33
22
Analog 3.3V Supply
AGND
15, 19
Analog Ground
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