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參數(shù)資料
| 型號： | DP83848C-MAU-EK |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 3/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION DP83848C |
| 標準包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng) |
| 已用 IC / 零件： | DP83848C |
| 已供物品： | 板 |
| 相關產(chǎn)品： | DP83848CVVX/NOPBTR-ND - TXRX ETHERNET PHYTER 48-LQFP DP83848CVV-ND - IC TXRX ETHERNET PHYTER 48-LQFP |
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10
DP
83
84
8C
RX_CLK
O
38
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive
clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock in-
put as the 50 MHz reference for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive
clocks for 10 Mb/s SNI mode.
RX_DV
S, O, PD
39
MII RECEIVE DATA VALID: Asserted high to indicate that valid
data is present on the corresponding RXD[3:0]. MII mode by de-
fault with internal pulldown.
RMII Synchronous Receive Data Valid: This signal provides the
RMII Receive Data Valid indication independent of Carrier Sense.
This pin is not used in SNI mode.
RX_ER
S, O, PU
41
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK
to indicate that an invalid symbol has been detected within a re-
ceived packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Assert high synchronously to X1 when-
ever it detects a media error and RXDV is asserted in 100 Mb/s
mode.
This pin is not required to be used by a MAC, in either MII or RMII
mode, since the Phy is required to corrupt data on a receive error.
This pin is not used in SNI mode.
RXD_0
RXD_1
RXD_2
RXD_3
S, O, PD
43
44
45
46
MII RECEIVE DATA: Nibble wide receive data signals driven syn-
chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz
for 10 Mb/s mode). RXD[3:0] signals contain valid data when
RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driv-
en synchronously to the X1 clock, 50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven syn-
chronously to the RX_CLK. RXD_0 contains valid data when CRS
is asserted. RXD[3:1] are not used in this mode.
CRS/CRS_DV
S, O, PU
40
MII CARRIER SENSE: Asserted high to indicate the receive me-
dium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal
combines the RMII Carrier and Receive Data Valid indications.
For a detailed description of this signal, see the RMII Specifica-
tion.
SNI CARRIER SENSE: Asserted high to indicate the receive me-
dium is non-idle. It is used to frame valid receive data on the
RXD_0 signal.
COL
S, O, PU
42
MII COLLISION DETECT: Asserted high to indicate detection of
a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this
pin is also asserted for a duration of approximately 1
s at the end
of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig-
nal is always logic 0. There is no heartbeat function during 10
Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL
signal is required. The MAC will recover CRS from the CRS_DV
signal and use that along with its TX_EN signal to determine col-
lision.
SNI COLLISION DETECT: Asserted high to indicate detection of
a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s SNI mode.
Signal Name
Type
Pin #
Description
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DP83848C-POE-EK | 功能描述:以太網(wǎng)開發(fā)工具 DP83848 POE CARD COMM TEMP RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DP83848CVV | 制造商:Texas Instruments 功能描述:IC, 10/100 ETHERNET PHY, SMD, LQFP48 |
| DP83848CVV/NOPB | 功能描述:以太網(wǎng) IC PHYTER COMMERCIAL TEMP SGL PORT RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| DP83848CVV/NOPB | 制造商:Texas Instruments 功能描述:Ethernet Transceiver |
| DP83848CVVX | 制造商:Texas Instruments 功能描述:PHY 1-CH 10Mbps/100Mbps 48-Pin LQFP T/R |
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