參數(shù)資料
型號: DS1865K
廠商: Maxim Integrated Products
文件頁數(shù): 17/67頁
文件大小: 0K
描述: KIT EVAL FOR DS1865
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,無源光學(xué)網(wǎng)絡(luò)(PON)
已用 IC / 零件: DS1865
DS1865
PON Triplexer Control and
Monitoring Circuit
24
____________________________________________________________________
Table 02h Register Map
TABLE 02h (PW2)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
<0> CONFIG0
<8>MODE
<4>T INDEX
<4> MOD DAC
<4> APC DAC
<4> V INDEX
<4> M4DAC
<10> DEVICE ID
<10> DEVICEVER
88
<8> CONFIG1
UPDATE
RATE
CONFIG
STARTUP
STEP
MOD
RANGING
DEVICE
ADDRESS
COMP
RANGING
RSHIFT1
RSHIFT0
90
<8> SCALE0
RESERVED
VCC SCALE
MON1 SCALE
MON2 SCALE
98
<8> SCALE1
MON3 SCALE
MON4 SCALE
RESERVED
A0
<8> OFFSET0
RESERVED
VCC OFFSET
MON1 OFFSET
MON2 OFFSET
A8
<8> OFFSET1
MON3 OFFSET
MON4 OFFSET
RESERVED
INTERNAL TEMP OFFSET*
B0
<9> PWD VALUE
PW1 MSW
PW1 LSW
PW2 MSW
PW2 LSW
B8
<8> INTERRUPT
FETG EN1
FETG EN0
TX-F EN1
TX-F EN0
HTXP
LTXP
HBIAS
MAX IBIAS
C0
<8> CNTL OUT
DPU
RESERVED
DAC1
RESERVED
M4 LUT CNTL
C8-F7
EMPTY
F8
<0> MAN IBIAS
<4> MAN IBIAS1 <4> MAN IBIAS0 <4> MAN_CNTL <10> BIAS DAC1 <10> BIAS DAC0
RESERVED
ACCESS CODE
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
Read Access
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
Write Access
See each
bit/byte
separately
PW2
N/A
All and
DS1865
hardware
PW2 +
mode bit
All
PW1
PW2
N/A
PW1
*
The final result must be XORed with BB40h before writing to this register.
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