參數(shù)資料
型號(hào): DS1865K
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 58/67頁(yè)
文件大?。?/td> 0K
描述: KIT EVAL FOR DS1865
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,無源光學(xué)網(wǎng)絡(luò)(PON)
已用 IC / 零件: DS1865
DS1865
PON Triplexer Control and
Monitoring Circuit
____________________________________________________________________
61
Table 02h, Register C0h: DPU
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
C0h
RESERVED
INV LOSI
MUX LOSI
D3 CNTL
D2 CNTL
D1 CNTL
D0 CNTL
bit7
bit0
Controls the power-on values for D3, D2, D1, and D0 output pins and mux and invertion of the LOSI pin.
Bit7:6
RESERVED
Bit5
INV LOSI: Inverts the buffered input pin LOSI to output pin D0 if MUX LOSI is set. If MUX LOSI is not
set then this bit’s value is a don’t care.
0 = (Default) noninverted LOSI to D0 pin.
1 = Inverted LOSI to D0 pin.
Bit4
MUX LOSI: chooses the control for D0 output pin.
0 = (Default) DO is controlled by bit D0 OUT found in Lower Memory, Register 78h.
1 = LOSI is buffered to D0 pin.
Bit3
D3 CNTL: At power-on, this value is loaded into bit D3 OUT of Lower Memory, Register 78h to
control the output pin D3.
Bit2
D2 CNTL: At power-on, this value is loaded into bit D2 OUT of Lower Memory, Register 78h to
control the output pin D2.
bit1
D1 CNTL: At power-on, this value is loaded into bit D1 OUT of Lower Memory, Register 78h to
control the output pin D1.
bit0
D0 CNTL: At power-on, this value is loaded into bit D0 OUT of Lower Memory, Register 78h to
control the output pin D0.
Table 02h, Register C1h to C3h: Reserved
FACTORY DEFAULT:
0000 0000h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register C4h: DAC1
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
C4h
2
7
2
6
2
5
2
4
2
3
2
1
2
0
bit7
bit0
Register to control DAC1.
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