參數(shù)資料
型號: DS1865K
廠商: Maxim Integrated Products
文件頁數(shù): 37/67頁
文件大?。?/td> 0K
描述: KIT EVAL FOR DS1865
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
主要目的: 電信,無源光學網(wǎng)絡(PON)
已用 IC / 零件: DS1865
DS1865
PON Triplexer Control and
Monitoring Circuit
42
____________________________________________________________________
Table 01h, Register 80h to F7h: PW1 EEPROM
POWER-ON VALUE
00h
READ ACCESS
PW1
WRITE ACCESS
PW1
MEMORY TYPE
Nonvolatile (EE)
80h-F7h
EE
bit7
bit0
EEPROM for PW1 level access.
Table 01h Register Descriptions
Table 01h, Register F8h: Alarm3
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
F8h
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
MON2 LO
bit7
bit0
Layout is identical to Alarm3 in Lower Memory, Register 70h with two exceptions.
1.
VCC low alarm is not set at power-on.
2.
These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register F9h: Alarm2
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE:
Volatile
F9h
MON3 HI
MON3 LO
MON4 HI
MON4 LO
RESERVED
bit7
bit0
Layout is identical to Alarm2 in Lower Memory, Register 71h with one exception.
1.
These bits are latched. They are cleared by power-down or a write with PW1 access.
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