參數(shù)資料
型號(hào)： DS2180AQN+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 10/35頁(yè)
文件大小： 0K
描述： IC TRANSCEIVER T1 44-PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 500
功能： 收發(fā)器
接口： T1
電路數(shù)： 1
電源電壓： 4.5 V ~ 5.5 V
電流 - 電源： 3mA
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
包括： 警報(bào)生成和檢測(cè)，B7 填充模式，B8ZS 模式，錯(cuò)誤檢測(cè)和計(jì)數(shù)器，“硬件”模式，透明模式
DS2180A
18 of 35
RSR: RECEIVE STATUS REGISTER Figure 17
(MSB)
(LSB)
BVCS
ECS
RYEL
RCL
FERR
B8ZSD
RBL
RLOS
SYMBOL
POSITION
NAME AND DESCRIPTION
BVCS
RSR.7
Bipolar Violation Count Saturation. Set when the 8-bit counter
at BVCR saturates.
ECS
RSR.6
Error Count Saturation. Set when either of the 4-bit counters at
ECR saturates.
RYEL
RSR.5
Receive Yellow Alarm. Set when yellow alarm detected.
(Detected yellow alarm format determined by CCR.4 and CCR.3.)
RCL
RSR.4
Receive Carrier Loss. Set when 32 consecutive 0’s appear at
RPOS and RNEG.
FERR
RSR.3
Frame Bit Error. Set when FT (193S) or FPS (193E) bit error
occurs.
B8ZSD
RSR.2
Bipolar Eight Zero Substitution Detect. Set when B8ZS code
word detected.
RBL
RSR.1
Receive Blue Alarm. Set when two consecutive frames have less
than three 0’s (total) in the data stream (F-bit positions not tested).
RLOS
RSR.0
Receive Loss of Sync. Set when resync is in process; if RCR.1=0,
RLOS transitions high on an OOF event or carrier loss indicating
auto resync.
RECEIVE ALARM REPORTING
Incoming serial data is monitored by the transceiver for alarm occurrences. Alarm conditions are reported
in two ways: via transitions on the alarm output pins and registered interrupt, in which the host controller
reads the RSR in response to an alarm-driven interrupt. Interrupts may be direct, in which the transceiver
demands service for a real-time alarm, or count-overflow triggered, in which an onboard alarm event
counter exceeds a user-programmed threshold. The user may mask individual alarm conditions by
clearing the appropriate bits in the receive interrupt mask register (RIMR).
ALARM SERVICING
The host controller must service the transceiver in order to clear an interrupt condition. Clearing
appropriate bits in the RIMR will unconditionally clear an interrupt. Direct interrupt (those driven from
real-time alarms) will be cleared when the RSR is directly read unless the alarm condition still exists.
Count-overflow interrupts (BVCS, ECS) are not cleared by a direct read of the RSR. They will be cleared
only when the user presets the appropriate count register to a value other than all 1’s. A burst read of the
RSR will not clear an interrupt condition.
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參數(shù)描述
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DS2181A 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2181A+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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