F
參數(shù)資料
型號(hào)： DS2180AQN+T&R
廠商： Maxim Integrated Products
文件頁數(shù)： 15/35頁
文件大小： 0K
描述： IC TRANSCEIVER T1 44-PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 500
功能： 收發(fā)器
接口： T1
電路數(shù)： 1
電源電壓： 4.5 V ~ 5.5 V
電流 - 電源： 3mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
包括： 警報(bào)生成和檢測(cè)，B7 填充模式，B8ZS 模式，錯(cuò)誤檢測(cè)和計(jì)數(shù)器，“硬件”模式，透明模式
DS2180A
22 of 35
4. RLOS transitions high during the F-bit time that caused an OOF event (any two of four consecutive
FT or FPS bits are in error) if auto-resync mode is selected (RCR.1=0). Resync will also occur when
loss of carrier is detected (RCL=1). When RCR.1=1, RLOS remains low until resync occurs,
regardless of OOF or carrier loss flags. In this situation, resync is initiated only when RCR.0
transitions low-to-high or the RST pin transitions high-low-high.
HARDWARE MODE
For preliminary system prototyping or applications which do not require the features offered by the serial
port, the transceiver can be reconfigured by the SPS pin. Tying SPS to VSS disables the serial port, clears
all internal registers except CCR and TCR and redefines pins 14 through 18 as mode control inputs. The
hardware mode allows device retrofit into existing applications where mode control and alarm
conditioning hardware is often designed with discrete logic.
HARDWARE COMMON CONTROL
In the hardware mode bits TCR.2, CCR.4, TCR.0, CCR.1 and CCR.2 map to pins 14 through 18. The
loop-back feature (bit CCR.0) is enabled by tying pins 17 (zero suppression) and 18 (B8ZS) to 1. (The
last states of pins 17 and 18 are latched as when both pins are taken high, preserving the current zero
suppression mode). Robbed bit signaling (bit TCR.4) is enabled for all channels. The user may tie TSER
to TABCD externally to disable signaling if so desired. Bit CCR.3 is forced to 0 which selects bit 2
yellow alarm in 193S framing. Contents of the RCR, as well as the remaining bit locations in the CCR
and TCR are cleared in the hardware mode. The RST input may be used to force immediate receiver
resync and has no effect on transmit.
HARDWARE MODE Table 6
PIN
NUMBER
REGISTER BIT
LOCATION
NAME AND DESCRIPTION
14 (16)
TCR-D2
193S – S-bit insertion
3
1 = external; 0 = internal
15 (17)
CCR-D4
Framing Mode Select.
1 = 193E; 0 = 193S
16 (18)
TCR-D0
Transmit Yellow Alarm
2 ,3
1 = enabled; 0 = disabled
17 (19)
CCR-D1
Zero Suppression
1
1 = bit 7 stuffing
0 = transparent
18 (20)
CCR-D2
B8ZS
1
1 = enabled; 0 = disabled
NOTES
1. Tying pins 17 and 18 high enables loopback in the hardware mode.
2. Bit 2 (193S) and data link (193E) yellow alarms are supported.
3. S-bit yellow alarm (193S) is not internally supported; however, the user may elect to insert external S
bits for alarm purposes.
4. Pin numbers for PLCC package are listed in parenthesis.
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