參數(shù)資料
型號(hào): DS2180AQN+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 35/35頁(yè)
文件大?。?/td> 0K
描述: IC TRANSCEIVER T1 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
功能: 收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 3mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
包括: 警報(bào)生成和檢測(cè),B7 填充模式,B8ZS 模式,錯(cuò)誤檢測(cè)和計(jì)數(shù)器,“硬件”模式,透明模式
DS2180A
9 of 35
TRANSMIT SIGNALING
When enabled (via TCR.4) channel signaling is inserted in frames 6 and 12 (193S) or in frames 6, 12, 18
and 24 (193E) in the 8
th bit position of every channel word. Signaling data is sampled at TABCD on the
falling edge of TCLK during bit 8 of each input word during signaling frames. Logical combination of
clocks TMO, TSIGFR and TSIGSEL allows external multiplexing of separate serial links for A, B or A,
B, C, D signaling sources.
TTR1–TTR3: TRANSMIT TRANSPARENCY REGISTERS Figure 6
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TTR3.7
CH1
TTR1.0
Transmit Transparent Registers. Each of these bit positions
represents a DS0 channel in the outgoing frame. When set, the
corresponding channel is transparent.
TIR1–TIR3: TRANSMIT IDLE REGISTERS Figure 7
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TIR3.7
CH1
TIR1.0
Transmit Idle Registers. Each of these bit positions represents a
DS0 channel in the outgoing frame. When set, the corresponding
channel will output an idle code format determined by TCR.2.
TRANSMIT CHANNEL TRANSPARENCY
Individual DS0 channels in the T1 frame may be programmed clear (no inserted robbed bit signaling and
no bit 7 zero suppression) by setting the appropriate bits in the transmit transparency registers. Channel
transparency is required in mixed voice/data or data-only environments such as ISDN, where data
integrity must be maintained.
TRANSMIT IDLE CODE INSERTION
Individual outgoing channels in the frame can be programmed with idle code by asserting the appropriate
bits in the transmit idle registers. One of two idle code formats, 7F (Hex) and FF (Hex) may be selected
by the user via TCR.3. If enabled, robbed bit signaling data is inserted into the idle channel, unless the
appropriate TTR bit is set for that channel. This feature eliminates external hardware currently required to
intercept and stuff unoccupied channels in the DS1 bit stream.
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