VSS
參數(shù)資料
型號(hào)： DS2180AQN+T&R
廠商： Maxim Integrated Products
文件頁數(shù)： 30/35頁
文件大?。?/td> 0K
描述： IC TRANSCEIVER T1 44-PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 500
功能： 收發(fā)器
接口： T1
電路數(shù)： 1
電源電壓： 4.5 V ~ 5.5 V
電流 - 電源： 3mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
包括： 警報(bào)生成和檢測，B7 填充模式，B8ZS 模式，錯(cuò)誤檢測和計(jì)數(shù)器，“硬件”模式，透明模式
DS2180A
4 of 35
POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
PIN
SYMBOL
TYPE
DESCRIPTION
20
VSS
-
Signal Ground.
0.0 volts.
32
TEST
I
Test Mode.
Tie to VSS for normal operation.
40
VDD
-
Positive Supply.
5.0 volts.
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN
SYMBOL
TYPE
DESCRIPTION
21
RYEL
0
Receive Yellow Alarm.
Transitions high when yellow alarm detected, goes low
when alarm clears.
22
RLINK
0
Receive Link Data.
Updated with extracted FDL data one RCLK before start of
odd frames (193E) and held until next update. Updated with extracted S-bit data one
RCLK before start of even frames (193S) and held until next update.
23
RLCLK
0
Receive Link Clock.
4 kHz demand clock for RLINK.
24
RCLK
I
Receive Clock.
1.544 MHz primary clock.
25
RCHCLK
O
Receive Channel Clock.
192 kHz clock identifies time slot (channel) boundaries.
26
RSER
O
Receive Serial Data.
Received NRZ serial data, updated on rising edges of RCLK.
27
RFSYNC
O
Receive Frame Sync.
Extracted 8 kHz clock, one RCLK wide, indicates F-Bit
position in each frame.
28
RMSYNC
O
Receive Multiframe Sync.
Extracted multiframe sync; edge indicates start of
multiframe, 50% duty cycle.
29
RABCD
O
Receive ABCD Signaling.
Extracted signaling data output, valid for each channel
time in signaling frames. In non-signaling frames, RABCD outputs the LSB of each
channel word.
30
RSIGFR
O
Receive Signaling Frame.
High during signaling frames, low during resync and
non-signaling frames.
31
RSIGSEL
O
Receive Signaling Select.
In 193E framing a .667 kHz clock which identifies
signaling frames A and C. A 1.33 kHz clock in 193S.
33
RST
I
Reset.
A high-low transition clears all internal registers and resets receive side
counters. A high-low-high transition will initiate a receive resync.
34
35
RPOS
RNEG
I
Receive Bipolar Data Inputs.
Samples on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
36
RCL
O
Receive Carrier Loss.
High if 32 consecutive 0's appear at RPOS and RNEG; goes
low after next 1.
37
RBV
O
Receive Bipolar Violation.
High during accused bit time at RSER if bipolar
violation detected, low otherwise.
38
RFER
O
Receive Frame Error.
High during F-Bit time when FT or FS errors occur (193S)
or when FPS or CRC errors occur (193E). Low during resync.
39
RLOS
O
Receive Loss of Sync.
Indicates sync status; high when internal resync is in
progress, low otherwise.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2180IND 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
DS2180Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver
DS2180QIND 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
DS2181A 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2181A+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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