參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 12/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
109 of 160
HSRA: HDLC STATUS REGISTER FRAMER A (Address = 01 Hex)
HSRB: HDLC STATUS REGISTER FRAMER B (Address = A1 Hex)
(MSB)
(LSB)
RBOC
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
RBOC
HSR.7
Receive BOC Detector Change of State. Set whenever the
BOC detector sees a change of state from a BOC Detected to a
No Valid Code seen or vice versa. The setting of this bit
prompt the user to read the RBOC register for details.
RPE
HSR.6
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as
a CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
RPS
HSR.5
Receive Packet Start. Set when the HDLC controller detects
an opening byte. The setting of this bit prompts the user to
read the RHIR register for details.
RHALF
HSR.4
Receive FIFO Half Full. Set when the receive 64–byte FIFO
fills beyond the half waypoint. The setting of this bit prompts
the user to read the RHIR register for details.
RNE
HSR.3
Receive FIFO Not Empty. Set when the receive 64–byte
FIFO has at least one byte available for a read. The setting of
this bit prompts the user to read the RHIR register for details.
THALF
HSR.2
Transmit FIFO Half Empty. Set when the transmit 64–byte
FIFO empties beyond the half waypoint. The setting of this bit
prompts the user to read the THIR register for details.
TNF
HSR.1
Transmit FIFO Not Full. Set when the transmit 64–byte
FIFO has at least one byte available. The setting of this bit
prompts the user to read the THIR register for details.
TMEND
HSR.0
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this
bit prompts the user to read the THIR register for details.
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
相關PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
DS21FF44N DATACOM, FRAMER, PBGA300
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
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